From 78c47fa50b903d5dcb4e07a5c048a35cbc2add9e Mon Sep 17 00:00:00 2001
From: Scott Michel <scottm@aero.org>
Date: Mon, 10 Mar 2008 16:58:52 +0000
Subject: [PATCH] Integer comparison tests for CellSPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/CellSPU/SPUISelDAGToDAG.cpp |   4 +-
 lib/Target/CellSPU/SPUISelLowering.cpp |  24 +-
 lib/Target/CellSPU/SPUISelLowering.h   |   2 +-
 lib/Target/CellSPU/SPUInstrInfo.td     | 215 ++++++++++++----
 test/CodeGen/CellSPU/icmp16.ll         | 340 +++++++++++++++++++++++++
 test/CodeGen/CellSPU/icmp32.ll         | 340 +++++++++++++++++++++++++
 test/CodeGen/CellSPU/icmp8.ll          | 277 ++++++++++++++++++++
 7 files changed, 1133 insertions(+), 69 deletions(-)
 create mode 100644 test/CodeGen/CellSPU/icmp16.ll
 create mode 100644 test/CodeGen/CellSPU/icmp32.ll
 create mode 100644 test/CodeGen/CellSPU/icmp8.ll

diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 6fad71471dc..1d4b28b4c53 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -41,14 +41,14 @@ namespace {
   bool
   isI64IntS10Immediate(ConstantSDNode *CN)
   {
-    return isS10Constant(CN->getValue());
+    return isS10Constant(CN->getSignExtended());
   }
 
   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
   bool
   isI32IntS10Immediate(ConstantSDNode *CN)
   {
-    return isS10Constant((int) CN->getValue());
+    return isS10Constant(CN->getSignExtended());
   }
 
 #if 0
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 6d0bd779e30..e04722ffe1e 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -244,21 +244,21 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
   setOperationAction(ISD::CTLZ , MVT::i32,   Legal);
   
   // SPU has a version of select
-  setOperationAction(ISD::SELECT, MVT::i1,   Expand);
-  setOperationAction(ISD::SELECT, MVT::i8,   Expand);
+  setOperationAction(ISD::SELECT, MVT::i1,   Promote);
+  setOperationAction(ISD::SELECT, MVT::i8,   Legal);
   setOperationAction(ISD::SELECT, MVT::i16,  Legal);
   setOperationAction(ISD::SELECT, MVT::i32,  Legal);
   setOperationAction(ISD::SELECT, MVT::i64,  Expand);
   setOperationAction(ISD::SELECT, MVT::f32,  Expand);
   setOperationAction(ISD::SELECT, MVT::f64,  Expand);
 
-  setOperationAction(ISD::SETCC, MVT::i1,   Expand);
-  setOperationAction(ISD::SETCC, MVT::i8,   Expand);
-  setOperationAction(ISD::SETCC, MVT::i16,  Legal);
-  setOperationAction(ISD::SETCC, MVT::i32,  Legal);
-  setOperationAction(ISD::SETCC, MVT::i64,  Expand);
-  setOperationAction(ISD::SETCC, MVT::f32,  Expand);
-  setOperationAction(ISD::SETCC, MVT::f64,  Expand);
+  setOperationAction(ISD::SETCC, MVT::i1,    Promote);
+  setOperationAction(ISD::SETCC, MVT::i8,    Legal);
+  setOperationAction(ISD::SETCC, MVT::i16,   Legal);
+  setOperationAction(ISD::SETCC, MVT::i32,   Legal);
+  setOperationAction(ISD::SETCC, MVT::i64,   Expand);
+  setOperationAction(ISD::SETCC, MVT::f32,   Expand);
+  setOperationAction(ISD::SETCC, MVT::f64,   Expand);
 
   // Zero extension and sign extension for i64 have to be
   // custom legalized
@@ -380,7 +380,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
   setOperationAction(ISD::XOR, MVT::v16i8, Custom);
   setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
 
-  setSetCCResultType(MVT::i32);
   setShiftAmountType(MVT::i32);
   setSetCCResultContents(ZeroOrOneSetCCResult);
   
@@ -449,6 +448,11 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
   return ((i != node_names.end()) ? i->second : 0);
 }
 
+MVT::ValueType
+SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
+  return Op.getValueType();
+}
+
 //===----------------------------------------------------------------------===//
 // Calling convention code:
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h
index b8f6ee3ea5b..d5bfac4ca75 100644
--- a/lib/Target/CellSPU/SPUISelLowering.h
+++ b/lib/Target/CellSPU/SPUISelLowering.h
@@ -104,7 +104,7 @@ namespace llvm {
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - Return the ValueType for ISD::SETCC
-    MVT::ValueType getSetCCResultType(const SDOperand &) const;
+    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
     
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index b76e03dc345..bd288d3bd6a 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -1392,7 +1392,7 @@ def XORHIr16:
       [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
 
 def XORIv4i32:
-    RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
+    RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
       "xori\t$rT, $rA, $val", IntegerOp,
       [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
                                      v4i32SExt10Imm:$val))]>;
@@ -1515,7 +1515,7 @@ def : SPUselbPat<v2i64, SELBv2i64>;
 
 class SelectConditional<RegisterClass rclass, SPUInstr inst>:
     Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
-        (inst rclass:$rCond, rclass:$rFalse, rclass:$rTrue)>;
+        (inst rclass:$rFalse, rclass:$rTrue, rclass:$rCond)>;
 
 def : SelectConditional<R32C, SELBr32>;
 def : SelectConditional<R16C, SELBr16>;
@@ -2875,12 +2875,33 @@ defm CLGTHI : CmpLGtrHalfwordImm;
 defm CLGT   : CmpLGtrWord;
 defm CLGTI  : CmpLGtrWordImm;
 
+//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
 // define a pattern to generate the right code, as a binary operator
 // (in a manner of speaking.)
+//
+// N.B.: This only matches the setcc set of conditionals. Special pattern
+// matching is used for select conditionals.
+//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
 
-class SETCCNegCond<PatFrag cond, RegisterClass rclass, dag pattern>:
-    Pat<(cond rclass:$rA, rclass:$rB), pattern>;
+class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
+                      SPUInstr xorinst, SPUInstr cmpare>:
+  Pat<(cond rclass:$rA, rclass:$rB),
+      (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
+
+class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
+                      PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
+  Pat<(cond rclass:$rA, (inttype immpred:$imm)),
+      (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
+
+def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
+def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
+
+def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
+def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
+
+def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
+def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
 
 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
                     SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
@@ -2895,64 +2916,146 @@ class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
         (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
                (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
 
-def CGTEQBr8:  SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
-def CGTEQBIr8: SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
-def CLTBr8:    SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
-def CLTBIr8:   SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
-def CLTEQr8:   Pat<(setle R8C:$rA, R8C:$rB),
-                   (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
-def CLTEQIr8:  Pat<(setle R8C:$rA, immU8:$imm),
-                   (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
+def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
+def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
+def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
+def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
+def : Pat<(setle R8C:$rA, R8C:$rB),
+          (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
+def :  Pat<(setle R8C:$rA, immU8:$imm),
+           (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
 
-def CGTEQHr16:  SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
-def CGTEQHIr16: SETCCBinOpImm<setge, R16C, i16ImmUns10, i16,
-                              ORr16, CGTHIr16, CEQHIr16>;
-def CLTHr16:    SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
-def CLTHIr16:   SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
-def CLTEQr16:   Pat<(setle R16C:$rA, R16C:$rB),
-                    (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
-def CLTEQIr16:  Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
-                    (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
+def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
+def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
+                    ORr16, CGTHIr16, CEQHIr16>;
+def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
+def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
+def : Pat<(setle R16C:$rA, R16C:$rB),
+          (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
+def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
+          (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
 
-def CGTEQHr32:  SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
-def CGTEQHIr32: SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
-                              ORr32, CGTIr32, CEQIr32>;
-def CLTr32:     SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
-def CLTIr32:    SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
-def CLTEQr32:   Pat<(setle R32C:$rA, R32C:$rB),
-                    (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
-def CLTEQIr32:  Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
-                    (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
+def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
+def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
+                    ORr32, CGTIr32, CEQIr32>;
+def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
+def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
+def : Pat<(setle R32C:$rA, R32C:$rB),
+          (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
+def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
+          (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
 
-def CLGTEQBr8:  SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
-def CLGTEQBIr8: SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
-def CLLTBr8:    SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
-def CLLTBIr8:   SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
-def CLLTEQr8:   Pat<(setule R8C:$rA, R8C:$rB),
-                     (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
-def CLLTEQIr8:  Pat<(setule R8C:$rA, immU8:$imm),
-                     (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
+def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
+def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
+def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
+def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
+def : Pat<(setule R8C:$rA, R8C:$rB),
+          (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
+def :  Pat<(setule R8C:$rA, immU8:$imm),
+           (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
 
-def CLGTEQHr16:  SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
-def CLGTEQHIr16: SETCCBinOpImm<setuge, R16C, i16ImmUns10, i16,
-                               ORr16, CLGTHIr16, CEQHIr16>;
-def CLLTHr16:    SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
-def CLLTHIr16:   SETCCBinOpImm<setult, R16C, immSExt8, i16, NORr16, CLGTHIr16, CEQHIr16>;
-def CLLTEQr16:   Pat<(setule R16C:$rA, R16C:$rB),
-                      (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
-def CLLTEQIr16:  Pat<(setule R16C:$rA, i16ImmUns10:$imm),
-                      (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
+def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
+def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
+                    ORr16, CLGTHIr16, CEQHIr16>;
+def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
+def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
+                    CLGTHIr16, CEQHIr16>;
+def : Pat<(setule R16C:$rA, R16C:$rB),
+          (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
+def :  Pat<(setule R16C:$rA, i16ImmUns10:$imm),
+           (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
 
+def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
+def : SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
+                    ORr32, CLGTIr32, CEQIr32>;
+def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
+def : SETCCBinOpImm<setult, R32C, immSExt8, i32, NORr32, CLGTIr32, CEQIr32>;
+def : Pat<(setule R32C:$rA, R32C:$rB),
+          (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
+def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
+          (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
 
-def CLGTEQHr32:  SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
-def CLGTEQHIr32: SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
-                               ORr32, CLGTIr32, CEQIr32>;
-def CLLTr32:     SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
-def CLLTIr32:    SETCCBinOpImm<setult, R32C, immSExt8, i32, NORr32, CLGTIr32, CEQIr32>;
-def CLLTEQr32:   Pat<(setule R32C:$rA, R32C:$rB),
-                      (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
-def CLLTEQIr32:  Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
-                      (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
+//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+// select conditional patterns:
+//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
+                       SPUInstr selinstr, SPUInstr cmpare>:
+  Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
+              rclass:$rTrue, rclass:$rFalse),
+      (selinstr rclass:$rTrue, rclass:$rFalse,
+		(cmpare rclass:$rA, rclass:$rB))>;
+
+class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
+                       PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
+  Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
+	      rclass:$rTrue, rclass:$rFalse),
+      (selinstr rclass:$rTrue, rclass:$rFalse,
+                (cmpare rclass:$rA, immpred:$imm))>;
+
+def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
+def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
+def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
+def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
+def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
+def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
+
+def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
+def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
+def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
+def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
+def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
+def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
+
+def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
+def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
+def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
+def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
+def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
+def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
+
+class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
+                     SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
+                     SPUInstr cmpOp2>:
+  Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
+              rclass:$rFalse, rclass:$rTrue),
+      (selinstr rclass:$rTrue, rclass:$rFalse,
+                (binop (cmpOp1 rclass:$rA, rclass:$rB),
+                       (cmpOp2 rclass:$rA, rclass:$rB)))>;
+
+class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
+                     ValueType inttype,
+                     SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
+                     SPUInstr cmpOp2>:
+    Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
+	        rclass:$rTrue, rclass:$rFalse),
+        (selinstr rclass:$rFalse, rclass:$rTrue,
+                  (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
+                         (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
+
+def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
+def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
+                     SELBr8, ORr8, CGTBIr8, CEQBIr8>;
+
+def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
+def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
+                     SELBr16, ORr16, CGTHIr16, CEQHIr16>;
+
+def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
+def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
+                     SELBr32, ORr32, CGTIr32, CEQIr32>;
+
+def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
+def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
+                     SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
+
+def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
+def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
+                     SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
+
+def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
+def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
+                     SELBr32, ORr32, CLGTIr32, CEQIr32>;
 
 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
 
diff --git a/test/CodeGen/CellSPU/icmp16.ll b/test/CodeGen/CellSPU/icmp16.ll
new file mode 100644
index 00000000000..4dc0ad89a4e
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp16.ll
@@ -0,0 +1,340 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; For "positive" comparisons:
+; selb $3, $6, $5, <i1>
+; selb $3, $5, $4, <i1>
+;
+; For "negative" comparisons, i.e., those where the result of the comparison
+; must be inverted (setne, for example):
+; selb $3, $5, $6, <i1>
+; selb $3, $4, $5, <i1>
+
+; i16 integer comparisons:
+define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp eq i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp eq i16 %arg1, %arg2
+       ret i1 %A
+}
+
+define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp eq i16 %arg1, 511
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_eq_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp eq i16 %arg1, -512
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_eq_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp eq i16 %arg1, -1
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_eq_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp eq i16 %arg1, 32768
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ne_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ne i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_ne_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ne i16 %arg1, %arg2
+       ret i1 %A
+}
+
+define i16 @icmp_ne_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ne i16 %arg1, 511
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ne_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ne i16 %arg1, -512
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ne_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ne i16 %arg1, -1
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ne_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ne i16 %arg1, 32768
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ugt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ugt i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_ugt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ugt i16 %arg1, %arg2
+       ret i1 %A
+}
+
+define i16 @icmp_ugt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ugt i16 %arg1, 511
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ugt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ugt i16 %arg1, 65534
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ugt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ugt i16 %arg1, 65024
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ugt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ugt i16 %arg1, 32768
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_uge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp uge i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_uge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp uge i16 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp uge i16 %arg1, <immed> can always be transformed into
+;;       icmp ugt i16 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i16 @icmp_ult_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ult i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_ult_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ult i16 %arg1, %arg2
+       ret i1 %A
+}
+
+define i16 @icmp_ult_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ult i16 %arg1, 511
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ult_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ult i16 %arg1, 65534
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ult_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ult i16 %arg1, 65024
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ult_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ult i16 %arg1, 32768
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_ule_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ule i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_ule_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp ule i16 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp ule i16 %arg1, <immed> can always be transformed into
+;;       icmp ult i16 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i16 @icmp_sgt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sgt i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_sgt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sgt i16 %arg1, %arg2
+       ret i1 %A
+}
+
+define i16 @icmp_sgt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sgt i16 %arg1, 511
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_sgt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sgt i16 %arg1, -1
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_sgt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sgt i16 %arg1, -512
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_sgt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sgt i16 %arg1, 32768
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_sge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sge i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_sge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sge i16 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp sge i16 %arg1, <immed> can always be transformed into
+;;       icmp sgt i16 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i16 @icmp_slt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp slt i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_slt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp slt i16 %arg1, %arg2
+       ret i1 %A
+}
+
+define i16 @icmp_slt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp slt i16 %arg1, 511
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_slt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp slt i16 %arg1, -512
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_slt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp slt i16 %arg1, -1
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_slt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp slt i16 %arg1, 32768
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i16 @icmp_sle_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sle i16 %arg1, %arg2
+       %B = select i1 %A, i16 %val1, i16 %val2
+       ret i16 %B
+}
+
+define i1 @icmp_sle_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+       %A = icmp sle i16 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp sle i16 %arg1, <immed> can always be transformed into
+;;       icmp slt i16 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
diff --git a/test/CodeGen/CellSPU/icmp32.ll b/test/CodeGen/CellSPU/icmp32.ll
new file mode 100644
index 00000000000..daa673b8d61
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp32.ll
@@ -0,0 +1,340 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; For "positive" comparisons:
+; selb $3, $6, $5, <i1>
+; selb $3, $5, $4, <i1>
+;
+; For "negative" comparisons, i.e., those where the result of the comparison
+; must be inverted (setne, for example):
+; selb $3, $5, $6, <i1>
+; selb $3, $4, $5, <i1>
+
+; i32 integer comparisons:
+define i32 @icmp_eq_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp eq i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_eq_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp eq i32 %arg1, %arg2
+       ret i1 %A
+}
+
+define i32 @icmp_eq_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp eq i32 %arg1, 511
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_eq_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp eq i32 %arg1, -512
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_eq_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp eq i32 %arg1, -1
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_eq_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp eq i32 %arg1, 32768
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ne_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ne i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_ne_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ne i32 %arg1, %arg2
+       ret i1 %A
+}
+
+define i32 @icmp_ne_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ne i32 %arg1, 511
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ne_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ne i32 %arg1, -512
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ne_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ne i32 %arg1, -1
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ne_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ne i32 %arg1, 32768
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ugt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ugt i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_ugt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ugt i32 %arg1, %arg2
+       ret i1 %A
+}
+
+define i32 @icmp_ugt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ugt i32 %arg1, 511
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ugt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ugt i32 %arg1, 4294966784
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ugt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ugt i32 %arg1, 4294967293
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ugt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ugt i32 %arg1, 32768
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_uge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp uge i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_uge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp uge i32 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp uge i32 %arg1, <immed> can always be transformed into
+;;       icmp ugt i32 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i32 @icmp_ult_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ult i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_ult_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ult i32 %arg1, %arg2
+       ret i1 %A
+}
+
+define i32 @icmp_ult_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ult i32 %arg1, 511
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ult_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ult i32 %arg1, 4294966784
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ult_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ult i32 %arg1, 4294967293
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ult i32 %arg1, 32768
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_ule_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ule i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_ule_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp ule i32 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp ule i32 %arg1, <immed> can always be transformed into
+;;       icmp ult i32 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i32 @icmp_sgt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sgt i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_sgt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sgt i32 %arg1, %arg2
+       ret i1 %A
+}
+
+define i32 @icmp_sgt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sgt i32 %arg1, 511
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_sgt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sgt i32 %arg1, 4294966784
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_sgt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sgt i32 %arg1, 4294967293
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_sgt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sgt i32 %arg1, 32768
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_sge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sge i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_sge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sge i32 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp sge i32 %arg1, <immed> can always be transformed into
+;;       icmp sgt i32 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i32 @icmp_slt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp slt i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_slt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp slt i32 %arg1, %arg2
+       ret i1 %A
+}
+
+define i32 @icmp_slt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp slt i32 %arg1, 511
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_slt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp slt i32 %arg1, -512
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_slt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp slt i32 %arg1, -1
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_slt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp slt i32 %arg1, 32768
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i32 @icmp_sle_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sle i32 %arg1, %arg2
+       %B = select i1 %A, i32 %val1, i32 %val2
+       ret i32 %B
+}
+
+define i1 @icmp_sle_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+       %A = icmp sle i32 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp sle i32 %arg1, <immed> can always be transformed into
+;;       icmp slt i32 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
diff --git a/test/CodeGen/CellSPU/icmp8.ll b/test/CodeGen/CellSPU/icmp8.ll
new file mode 100644
index 00000000000..fd556d01131
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp8.ll
@@ -0,0 +1,277 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; For "positive" comparisons:
+; selb $3, $6, $5, <i1>
+; selb $3, $5, $4, <i1>
+;
+; For "negative" comparisons, i.e., those where the result of the comparison
+; must be inverted (setne, for example):
+; selb $3, $5, $6, <i1>
+; selb $3, $4, $5, <i1>
+
+; i8 integer comparisons:
+define i8 @icmp_eq_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp eq i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_eq_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp eq i8 %arg1, %arg2
+       ret i1 %A
+}
+
+define i8 @icmp_eq_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp eq i8 %arg1, 127
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_eq_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp eq i8 %arg1, -128
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_eq_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp eq i8 %arg1, -1
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_ne_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ne i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_ne_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ne i8 %arg1, %arg2
+       ret i1 %A
+}
+
+define i8 @icmp_ne_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ne i8 %arg1, 127
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_ne_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ne i8 %arg1, -128
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_ne_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ne i8 %arg1, -1
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_ugt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ugt i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_ugt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ugt i8 %arg1, %arg2
+       ret i1 %A
+}
+
+define i8 @icmp_ugt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ugt i8 %arg1, 126
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_uge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp uge i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_uge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp uge i8 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp uge i8 %arg1, <immed> can always be transformed into
+;;       icmp ugt i8 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i8 @icmp_ult_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ult i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_ult_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ult i8 %arg1, %arg2
+       ret i1 %A
+}
+
+define i8 @icmp_ult_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ult i8 %arg1, 253
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_ult_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ult i8 %arg1, 129
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_ule_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ule i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_ule_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp ule i8 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp ule i8 %arg1, <immed> can always be transformed into
+;;       icmp ult i8 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i8 @icmp_sgt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sgt i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_sgt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sgt i8 %arg1, %arg2
+       ret i1 %A
+}
+
+define i8 @icmp_sgt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sgt i8 %arg1, 127
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_sgt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sgt i8 %arg1, -1
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_sgt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sgt i8 %arg1, -128
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_sge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sge i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_sge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sge i8 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp sge i8 %arg1, <immed> can always be transformed into
+;;       icmp sgt i8 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i8 @icmp_slt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp slt i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_slt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp slt i8 %arg1, %arg2
+       ret i1 %A
+}
+
+define i8 @icmp_slt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp slt i8 %arg1, 127
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_slt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp slt i8 %arg1, -128
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_slt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp slt i8 %arg1, -1
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i8 @icmp_sle_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sle i8 %arg1, %arg2
+       %B = select i1 %A, i8 %val1, i8 %val2
+       ret i8 %B
+}
+
+define i1 @icmp_sle_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+       %A = icmp sle i8 %arg1, %arg2
+       ret i1 %A
+}
+
+;; Note: icmp sle i8 %arg1, <immed> can always be transformed into
+;;       icmp slt i8 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+