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When there is a 2-instruction spill sequence, record

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the second (store) instruction in SpillSlotToUsesMap
consistently.  I don't think this matters functionally,
but it's cleaner and Evan wants it this way.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85463 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2009-10-29 01:15:40 +00:00
parent 8bedf97f68
commit 78c5cdaf2a
1 changed files with 3 additions and 2 deletions
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5
lib/CodeGen/VirtRegRewriter.cpp
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@@ -1432,7 +1432,7 @@ private:
MachineBasicBlock::iterator oldNextMII = next(MII); MachineBasicBlock::iterator oldNextMII = next(MII);
TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
MachineInstr *StoreMI = next(MII); MachineInstr *StoreMI = prior(oldNextMII);
VRM.addSpillSlotUse(StackSlot, StoreMI); VRM.addSpillSlotUse(StackSlot, StoreMI);
DEBUG(errs() << "Store:\t" << *StoreMI); DEBUG(errs() << "Store:\t" << *StoreMI);
@@ -1751,8 +1751,9 @@ private:
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
unsigned Phys = VRM.getPhys(VirtReg); unsigned Phys = VRM.getPhys(VirtReg);
int StackSlot = VRM.getStackSlot(VirtReg); int StackSlot = VRM.getStackSlot(VirtReg);
MachineBasicBlock::iterator oldNextMII = next(MII);
TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
MachineInstr *StoreMI = next(MII); MachineInstr *StoreMI = prior(oldNextMII);
VRM.addSpillSlotUse(StackSlot, StoreMI); VRM.addSpillSlotUse(StackSlot, StoreMI);
DEBUG(errs() << "Store:\t" << *StoreMI); DEBUG(errs() << "Store:\t" << *StoreMI);
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);