Initial checkin of codegen infrastructure for LLVM-JIT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4282 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-10-25 22:54:41 +00:00
parent 2ee9aa1072
commit 78cee7e7ab
3 changed files with 109 additions and 1 deletions

76
lib/CodeGen/MFunction.cpp Normal file
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//===-- MFunction.cpp - Implementation code for the MFunction class -------===//
//
// This file contains a printer that converts from our internal representation
// of LLVM code to a nice human readable form that is suitable for debuggging.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MFunction.h"
#include "llvm/Target/MInstructionInfo.h"
#include "llvm/Target/MRegisterInfo.h"
#include <iostream>
static void printMRegister(unsigned RegNo, const MRegisterInfo &MRI,
std::ostream &OS) {
if (RegNo < MRegisterInfo::FirstVirtualRegister) {
OS << "%" << MRI[RegNo].Name; // Hard registers are prefixed with %
} else {
OS << "reg" << RegNo; // SSA registers are printed with 'reg' prefix
}
}
static void printMInstruction(const MInstruction &MI, std::ostream &OS,
const MInstructionInfo &MII) {
const MRegisterInfo &MRI = MII.getRegisterInfo();
OS << "\t";
if (MI.getDestinationReg() != MRegisterInfo::NoRegister) {// Produces a value?
printMRegister(MI.getDestinationReg(), MRI, OS);
OS << " = ";
}
OS << MII[MI.getOpcode()].Name << " ";
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
if (i != 0) OS << ", ";
switch (MI.getOperandInterpretation(i)) {
case MOperand::Register:
printMRegister(MI.getRegisterOperand(i), MRI, OS);
break;
case MOperand::SignExtImmediate:
OS << MI.getSignExtOperand(i) << "s";
break;
case MOperand::ZeroExtImmediate:
OS << MI.getZeroExtOperand(i) << "z";
break;
case MOperand::PCRelativeDisp:
if (MI.getPCRelativeOperand(i) >= 0)
OS << "pc+" << MI.getPCRelativeOperand(i);
else
OS << "pc" << MI.getPCRelativeOperand(i);
break;
default:
OS << "*UNKNOWN OPERAND INTERPRETATION*";
break;
}
}
OS << "\n";
}
/// print - Provide a way to get a simple debugging dump. This dumps the
/// machine code in a simple "assembly" language that is not really suitable
/// for an assembler, but is useful for debugging. This is completely target
/// independant.
///
void MFunction::print(std::ostream &OS, const MInstructionInfo &MII) const {
for (const_iterator I = begin(), E = end(); I != E; ++I) {
for (MBasicBlock::const_iterator II = I->begin(), IE = I->end();
II != IE; ++II)
printMInstruction(*II, OS, MII);
OS << "\n"; // blank line between basic blocks...
}
}
void MFunction::dump(const MInstructionInfo &MII) const {
print(std::cerr, MII);
}

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//===-- MInstruction.cpp - Implementation code for the MInstruction class -===//
//
// This file contains a printer that converts from our internal representation
// of LLVM code to a nice human readable form that is suitable for debuggging.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MBasicBlock.h"
/// MInstruction ctor - Create a new instruction, and append it to the
/// specified basic block.
///
MInstruction::MInstruction(MBasicBlock *BB, unsigned O, unsigned D)
: Opcode(O), Dest(D) {
// Add this instruction to the specified basic block
BB->getInstList().push_back(this);
}
/// addOperand - Add a new operand to the instruction with the specified value
/// and interpretation.
///
void MInstruction::addOperand(unsigned Value, MOperand::Interpretation Ty) {
if (Operands.size() < 4) {
OperandInterpretation[Operands.size()] = Ty; // Save interpretation
} else {
assert(Ty == MOperand::Register &&
"Trying to add 5th operand that is not a register to MInstruction!");
}
Operands.push_back(Value);
}

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LEVEL = ../..
PARALLEL_DIRS = PreOpts InstrSelection InstrSched RegAlloc PostOpts Mapping
LIBRARYNAME = codegen
include $(LEVEL)/Makefile.common