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Initial checkin of codegen infrastructure for LLVM-JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4282 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/CodeGen/MFunction.cpp
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76
lib/CodeGen/MFunction.cpp
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//===-- MFunction.cpp - Implementation code for the MFunction class -------===//
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//
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// This file contains a printer that converts from our internal representation
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// of LLVM code to a nice human readable form that is suitable for debuggging.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MFunction.h"
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#include "llvm/Target/MInstructionInfo.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include <iostream>
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static void printMRegister(unsigned RegNo, const MRegisterInfo &MRI,
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std::ostream &OS) {
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if (RegNo < MRegisterInfo::FirstVirtualRegister) {
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OS << "%" << MRI[RegNo].Name; // Hard registers are prefixed with %
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} else {
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OS << "reg" << RegNo; // SSA registers are printed with 'reg' prefix
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}
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}
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static void printMInstruction(const MInstruction &MI, std::ostream &OS,
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const MInstructionInfo &MII) {
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const MRegisterInfo &MRI = MII.getRegisterInfo();
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OS << "\t";
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if (MI.getDestinationReg() != MRegisterInfo::NoRegister) {// Produces a value?
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printMRegister(MI.getDestinationReg(), MRI, OS);
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OS << " = ";
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}
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OS << MII[MI.getOpcode()].Name << " ";
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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if (i != 0) OS << ", ";
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switch (MI.getOperandInterpretation(i)) {
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case MOperand::Register:
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printMRegister(MI.getRegisterOperand(i), MRI, OS);
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break;
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case MOperand::SignExtImmediate:
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OS << MI.getSignExtOperand(i) << "s";
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break;
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case MOperand::ZeroExtImmediate:
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OS << MI.getZeroExtOperand(i) << "z";
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break;
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case MOperand::PCRelativeDisp:
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if (MI.getPCRelativeOperand(i) >= 0)
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OS << "pc+" << MI.getPCRelativeOperand(i);
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else
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OS << "pc" << MI.getPCRelativeOperand(i);
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break;
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default:
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OS << "*UNKNOWN OPERAND INTERPRETATION*";
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break;
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}
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}
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OS << "\n";
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}
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/// print - Provide a way to get a simple debugging dump. This dumps the
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/// machine code in a simple "assembly" language that is not really suitable
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/// for an assembler, but is useful for debugging. This is completely target
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/// independant.
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///
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void MFunction::print(std::ostream &OS, const MInstructionInfo &MII) const {
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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for (MBasicBlock::const_iterator II = I->begin(), IE = I->end();
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II != IE; ++II)
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printMInstruction(*II, OS, MII);
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OS << "\n"; // blank line between basic blocks...
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}
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}
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void MFunction::dump(const MInstructionInfo &MII) const {
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print(std::cerr, MII);
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}
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31
lib/CodeGen/MInstruction.cpp
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lib/CodeGen/MInstruction.cpp
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//===-- MInstruction.cpp - Implementation code for the MInstruction class -===//
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//
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// This file contains a printer that converts from our internal representation
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// of LLVM code to a nice human readable form that is suitable for debuggging.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MBasicBlock.h"
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/// MInstruction ctor - Create a new instruction, and append it to the
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/// specified basic block.
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///
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MInstruction::MInstruction(MBasicBlock *BB, unsigned O, unsigned D)
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: Opcode(O), Dest(D) {
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// Add this instruction to the specified basic block
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BB->getInstList().push_back(this);
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}
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/// addOperand - Add a new operand to the instruction with the specified value
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/// and interpretation.
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///
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void MInstruction::addOperand(unsigned Value, MOperand::Interpretation Ty) {
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if (Operands.size() < 4) {
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OperandInterpretation[Operands.size()] = Ty; // Save interpretation
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} else {
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assert(Ty == MOperand::Register &&
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"Trying to add 5th operand that is not a register to MInstruction!");
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}
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Operands.push_back(Value);
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}
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@ -1,4 +1,5 @@
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LEVEL = ../..
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PARALLEL_DIRS = PreOpts InstrSelection InstrSched RegAlloc PostOpts Mapping
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LIBRARYNAME = codegen
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include $(LEVEL)/Makefile.common
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