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If val# def is ~0U, meaning it's defined by a PHI, and it's previously split, spill before the barrier because it's impossible to determine if all the defs are spilled in the same spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58129 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -527,21 +527,23 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
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int SS;
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int SS;
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unsigned SpillIndex = 0;
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unsigned SpillIndex = 0;
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MachineInstr *SpillMI = NULL;
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MachineInstr *SpillMI = NULL;
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if (isAlreadySplit(CurrLI->reg, ValNo->id, SS)) {
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bool PrevSpilled = isAlreadySplit(CurrLI->reg, ValNo->id, SS);
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// If it's already split, just restore the value. There is no need to spill
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if (ValNo->def == ~0U) {
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// the def again.
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} else if (ValNo->def == ~0U) {
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// If it's defined by a phi, we must split just before the barrier.
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// If it's defined by a phi, we must split just before the barrier.
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MachineBasicBlock::iterator SpillPt =
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MachineBasicBlock::iterator SpillPt =
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findSpillPoint(BarrierMBB, Barrier, RefsInMBB, SpillIndex);
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findSpillPoint(BarrierMBB, Barrier, RefsInMBB, SpillIndex);
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if (SpillPt == BarrierMBB->begin())
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if (SpillPt == BarrierMBB->begin())
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return false; // No gap to insert spill.
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return false; // No gap to insert spill.
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// Add spill.
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// Add spill.
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SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
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if (!PrevSpilled)
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// If previously split, reuse the spill slot.
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SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
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TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
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TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
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SpillMI = prior(SpillPt);
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SpillMI = prior(SpillPt);
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LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
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LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
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} else {
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} else if (!PrevSpilled) {
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// If it's already split, just restore the value. There is no need to spill
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// the def again.
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// Check if it's possible to insert a spill after the def MI.
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// Check if it's possible to insert a spill after the def MI.
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MachineBasicBlock::iterator SpillPt =
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MachineBasicBlock::iterator SpillPt =
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findNextEmptySlot(DefMBB, DefMI, SpillIndex);
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findNextEmptySlot(DefMBB, DefMI, SpillIndex);
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@ -549,8 +551,8 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
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return false; // No gap to insert spill.
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return false; // No gap to insert spill.
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SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
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SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
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// Add spill. The store instruction kills the register if def is before the
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// Add spill. The store instruction kills the register if def is before
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// barrier in the barrier block.
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// the barrier in the barrier block.
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TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
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TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
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DefMBB == BarrierMBB, SS, RC);
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DefMBB == BarrierMBB, SS, RC);
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SpillMI = prior(SpillPt);
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SpillMI = prior(SpillPt);
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@ -567,7 +569,7 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
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// If live interval is spilled in the same block as the barrier, just
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// If live interval is spilled in the same block as the barrier, just
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// create a hole in the interval.
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// create a hole in the interval.
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if (!DefMBB ||
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if (!DefMBB ||
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(SpillIndex && SpillMI->getParent() == BarrierMBB)) {
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(SpillMI && SpillMI->getParent() == BarrierMBB)) {
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UpdateIntervalForSplit(ValNo, LIs->getUseIndex(SpillIndex)+1,
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UpdateIntervalForSplit(ValNo, LIs->getUseIndex(SpillIndex)+1,
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LIs->getDefIndex(RestoreIndex));
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LIs->getDefIndex(RestoreIndex));
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24
test/CodeGen/X86/pre-split4.ll
Normal file
24
test/CodeGen/X86/pre-split4.ll
Normal file
@ -0,0 +1,24 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
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; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 4
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define i32 @main(i32 %argc, i8** %argv) nounwind {
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entry:
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br label %bb
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bb: ; preds = %bb, %entry
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%k.0.reg2mem.0 = phi double [ 1.000000e+00, %entry ], [ %6, %bb ] ; <double> [#uses=2]
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%Flint.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %5, %bb ] ; <double> [#uses=1]
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%twoThrd.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] ; <double> [#uses=1]
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%0 = tail call double @llvm.pow.f64(double 0x3FE5555555555555, double 0.000000e+00) ; <double> [#uses=1]
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%1 = add double %0, %twoThrd.0.reg2mem.0 ; <double> [#uses=1]
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%2 = tail call double @sin(double %k.0.reg2mem.0) nounwind readonly ; <double> [#uses=1]
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%3 = mul double 0.000000e+00, %2 ; <double> [#uses=1]
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%4 = fdiv double 1.000000e+00, %3 ; <double> [#uses=1]
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%5 = add double %4, %Flint.0.reg2mem.0 ; <double> [#uses=1]
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%6 = add double %k.0.reg2mem.0, 1.000000e+00 ; <double> [#uses=1]
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br label %bb
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}
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declare double @llvm.pow.f64(double, double) nounwind readonly
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declare double @sin(double) nounwind readonly
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