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need to fix 'make check' tests first. revert for a moment.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-03-25 23:34:05 +00:00
parent bd17bc96bf
commit 78e496e165
2 changed files with 16 additions and 11 deletions
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13
lib/Target/ARM/ARM.td
View File

@ -49,14 +49,8 @@ def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
// FIXME: Currently, this is only flagged for Cortex-A8. It may be true for // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
// others as well. We should do more benchmarking and confirm one way or // others as well. We should do more benchmarking and confirm one way or
// the other. // the other.
def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true", def HasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
"Disable VFP MAC instructions">; "Disable VFP MAC instructions">;
// Some processors benefit from using NEON instructions for scalar
// single-precision FP operations.
def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
"true",
"Use NEON for single precision FP">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ARM Processors supported. // ARM Processors supported.
@ -121,8 +115,7 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries,
// V7 Processors. // V7 Processors.
def : Processor<"cortex-a8", CortexA8Itineraries, def : Processor<"cortex-a8", CortexA8Itineraries,
[ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx, [ArchV7A, FeatureThumb2, FeatureNEON, HasSlowVMLx]>;
FeatureNEONForFP]>;
def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

14
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -22,6 +22,10 @@ using namespace llvm;
static cl::opt<bool> static cl::opt<bool>
ReserveR9("arm-reserve-r9", cl::Hidden, ReserveR9("arm-reserve-r9", cl::Hidden,
cl::desc("Reserve R9, making it unavailable as GPR")); cl::desc("Reserve R9, making it unavailable as GPR"));
static cl::opt<bool>
UseNEONFP("arm-use-neon-fp",
cl::desc("Use NEON for single-precision FP"),
cl::init(false), cl::Hidden);
static cl::opt<bool> static cl::opt<bool>
UseMOVT("arm-use-movt", UseMOVT("arm-use-movt",
@ -31,7 +35,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
bool isT) bool isT)
: ARMArchVersion(V4) : ARMArchVersion(V4)
, ARMFPUType(None) , ARMFPUType(None)
, UseNEONForSinglePrecisionFP(false) , UseNEONForSinglePrecisionFP(UseNEONFP)
, SlowVMLx(false) , SlowVMLx(false)
, IsThumb(isT) , IsThumb(isT)
, ThumbMode(Thumb1) , ThumbMode(Thumb1)
@ -112,6 +116,14 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
if (!isThumb() || hasThumb2()) if (!isThumb() || hasThumb2())
PostRAScheduler = true; PostRAScheduler = true;
// Set CPU specific features.
if (CPUString == "cortex-a8") {
// On Cortex-a8, it's faster to perform some single-precision FP
// operations with NEON instructions.
if (UseNEONFP.getPosition() == 0)
UseNEONForSinglePrecisionFP = true;
}
} }
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.