6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

Remove the isMoveInstr() hook.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-07-16 22:35:46 +00:00
parent 2aaa98da76
commit 78e6e00922
28 changed files with 0 additions and 630 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
docs/WritingAnLLVMBackend.html
View File

@ -1299,9 +1299,6 @@ implementation in <tt>SparcInstrInfo.cpp</tt>:
</p>
<ul>
<li><tt>isMoveInstr</tt> &mdash; Return true if the instruction is a register to
register move; false, otherwise.</li>
<li><tt>isLoadFromStackSlot</tt> &mdash; If the specified machine instruction is
a direct load from a stack slot, return the register number of the
destination and the <tt>FrameIndex</tt> of the stack slot.</li>

9
include/llvm/Target/TargetInstrInfo.h
View File

@ -92,15 +92,6 @@ private:
AliasAnalysis *AA) const;
public:
/// isMoveInstr - Return true if the instruction is a register to register
/// move and return the source and dest operands and their sub-register
/// indices by reference.
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& SrcReg, unsigned& DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
return false;
}
/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
/// extension instruction. That is, it's like a copy where it's legal for the
/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns

42
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -573,48 +573,6 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
return 0; // Not reached
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
bool
ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
switch (MI.getOpcode()) {
default: break;
case ARM::VMOVS:
case ARM::VMOVD:
case ARM::VMOVDneon:
case ARM::VMOVQ:
case ARM::VMOVQQ : {
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
SrcSubIdx = MI.getOperand(1).getSubReg();
DstSubIdx = MI.getOperand(0).getSubReg();
return true;
}
case ARM::MOVr:
case ARM::MOVr_TC:
case ARM::tMOVr:
case ARM::tMOVgpr2tgpr:
case ARM::tMOVtgpr2gpr:
case ARM::tMOVgpr2gpr:
case ARM::t2MOVr: {
assert(MI.getDesc().getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"Invalid ARM MOV instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
SrcSubIdx = MI.getOperand(1).getSubReg();
DstSubIdx = MI.getOperand(0).getSubReg();
return true;
}
}
return false;
}
unsigned
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {

6
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -262,12 +262,6 @@ public:
///
virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,

26
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -27,32 +27,6 @@ AlphaInstrInfo::AlphaInstrInfo()
RI(*this) { }
bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg, unsigned& destReg,
unsigned& SrcSR, unsigned& DstSR) const {
unsigned oc = MI.getOpcode();
if (oc == Alpha::BISr ||
oc == Alpha::CPYSS ||
oc == Alpha::CPYST ||
oc == Alpha::CPYSSt ||
oc == Alpha::CPYSTs) {
// or r1, r2, r2
// cpys(s|t) r1 r2 r2
assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
MI.getOperand(2).isReg() &&
"invalid Alpha BIS instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
SrcSR = DstSR = 0;
return true;
}
}
return false;
}
unsigned
AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {

6
lib/Target/Alpha/AlphaInstrInfo.h
View File

@ -30,12 +30,6 @@ public:
///
virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,

28
lib/Target/Blackfin/BlackfinInstrInfo.cpp
View File

@ -28,34 +28,6 @@ BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
RI(ST, *this),
Subtarget(ST) {}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
bool BlackfinInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg,
unsigned &DstReg,
unsigned &SrcSR,
unsigned &DstSR) const {
SrcSR = DstSR = 0; // No sub-registers.
switch (MI.getOpcode()) {
case BF::MOVE:
case BF::MOVE_ncccc:
case BF::MOVE_ccncc:
case BF::MOVECC_zext:
case BF::MOVECC_nz:
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
case BF::SLL16i:
if (MI.getOperand(2).getImm()!=0)
return false;
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
default:
return false;
}
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

4
lib/Target/Blackfin/BlackfinInstrInfo.h
View File

@ -30,10 +30,6 @@ namespace llvm {
/// always be able to get register info as well (through this method).
virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;

142
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -54,148 +54,6 @@ SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
RI(*TM.getSubtargetImpl(), *this)
{ /* NOP */ }
bool
SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg,
unsigned& SrcSR, unsigned& DstSR) const {
SrcSR = DstSR = 0; // No sub-registers.
switch (MI.getOpcode()) {
default:
break;
case SPU::ORIv4i32:
case SPU::ORIr32:
case SPU::ORHIv8i16:
case SPU::ORHIr16:
case SPU::ORHIi8i16:
case SPU::ORBIv16i8:
case SPU::ORBIr8:
case SPU::ORIi16i32:
case SPU::ORIi8i32:
case SPU::AHIvec:
case SPU::AHIr16:
case SPU::AIv4i32:
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
MI.getOperand(2).isImm() &&
"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
break;
case SPU::AIr32:
assert(MI.getNumOperands() == 3 &&
"wrong number of operands to AIr32");
if (MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
(MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0)) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
break;
case SPU::LRr8:
case SPU::LRr16:
case SPU::LRr32:
case SPU::LRf32:
case SPU::LRr64:
case SPU::LRf64:
case SPU::LRr128:
case SPU::LRv16i8:
case SPU::LRv8i16:
case SPU::LRv4i32:
case SPU::LRv4f32:
case SPU::LRv2i64:
case SPU::LRv2f64:
case SPU::ORv16i8_i8:
case SPU::ORv8i16_i16:
case SPU::ORv4i32_i32:
case SPU::ORv2i64_i64:
case SPU::ORv4f32_f32:
case SPU::ORv2f64_f64:
case SPU::ORi8_v16i8:
case SPU::ORi16_v8i16:
case SPU::ORi32_v4i32:
case SPU::ORi64_v2i64:
case SPU::ORf32_v4f32:
case SPU::ORf64_v2f64:
/*
case SPU::ORi128_r64:
case SPU::ORi128_f64:
case SPU::ORi128_r32:
case SPU::ORi128_f32:
case SPU::ORi128_r16:
case SPU::ORi128_r8:
*/
case SPU::ORi128_vec:
/*
case SPU::ORr64_i128:
case SPU::ORf64_i128:
case SPU::ORr32_i128:
case SPU::ORf32_i128:
case SPU::ORr16_i128:
case SPU::ORr8_i128:
*/
case SPU::ORvec_i128:
/*
case SPU::ORr16_r32:
case SPU::ORr8_r32:
case SPU::ORf32_r32:
case SPU::ORr32_f32:
case SPU::ORr32_r16:
case SPU::ORr32_r8:
case SPU::ORr16_r64:
case SPU::ORr8_r64:
case SPU::ORr64_r16:
case SPU::ORr64_r8:
*/
case SPU::ORr64_r32:
case SPU::ORr32_r64:
case SPU::ORf32_r32:
case SPU::ORr32_f32:
case SPU::ORf64_r64:
case SPU::ORr64_f64: {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid SPU OR<type>_<vec> or LR instruction!");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
break;
}
case SPU::ORv16i8:
case SPU::ORv8i16:
case SPU::ORv4i32:
case SPU::ORv2i64:
case SPU::ORr8:
case SPU::ORr16:
case SPU::ORr32:
case SPU::ORr64:
case SPU::ORr128:
case SPU::ORf32:
case SPU::ORf64:
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
MI.getOperand(2).isReg() &&
"invalid SPU OR(vec|r32|r64|gprc) instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
break;
}
return false;
}
unsigned
SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {

6
lib/Target/CellSPU/SPUInstrInfo.h
View File

@ -32,12 +32,6 @@ namespace llvm {
///
virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,

35
lib/Target/MBlaze/MBlazeInstrInfo.cpp
View File

@ -30,41 +30,6 @@ static bool isZeroImm(const MachineOperand &op) {
return op.isImm() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
bool MBlazeInstrInfo::
isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
// add $dst, $src, $zero || addu $dst, $zero, $src
// or $dst, $src, $zero || or $dst, $zero, $src
if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) {
if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (MI.getOperand(2).isReg() &&
MI.getOperand(2).getReg() == MBlaze::R0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
}
// addi $dst, $src, 0
// ori $dst, $src, 0
if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI)) {
if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
}
return false;
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

6
lib/Target/MBlaze/MBlazeInstrInfo.h
View File

@ -173,12 +173,6 @@ public:
///
virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

21
lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -99,27 +99,6 @@ void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc));
}
bool
MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
switch (MI.getOpcode()) {
default:
return false;
case MSP430::MOV8rr:
case MSP430::MOV16rr:
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid register-register move instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
}
}
bool
MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,

4
lib/Target/MSP430/MSP430InstrInfo.h
View File

@ -54,10 +54,6 @@ public:
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
bool isMoveInstr(const MachineInstr& MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill,

47
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -30,53 +30,6 @@ static bool isZeroImm(const MachineOperand &op) {
return op.isImm() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
bool MipsInstrInfo::
isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const
{
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
// addu $dst, $src, $zero || addu $dst, $zero, $src
// or $dst, $src, $zero || or $dst, $zero, $src
if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
if (MI.getOperand(1).getReg() == Mips::ZERO) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (MI.getOperand(2).getReg() == Mips::ZERO) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
}
// mov $fpDst, $fpSrc
// mfc $gpDst, $fpSrc
// mtc $fpDst, $gpSrc
if (MI.getOpcode() == Mips::FMOV_S32 ||
MI.getOpcode() == Mips::FMOV_D32 ||
MI.getOpcode() == Mips::MFC1 ||
MI.getOpcode() == Mips::MTC1 ||
MI.getOpcode() == Mips::MOVCCRToCCR) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
// addiu $dst, $src, 0
if (MI.getOpcode() == Mips::ADDiu) {
if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
}
return false;
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

6
lib/Target/Mips/MipsInstrInfo.h
View File

@ -174,12 +174,6 @@ public:
///
virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

15
lib/Target/PIC16/PIC16InstrInfo.cpp
View File

@ -167,21 +167,6 @@ void PIC16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc));
}
bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DestReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
if (MI.getOpcode() == PIC16::copy_fsr
|| MI.getOpcode() == PIC16::copy_w) {
DestReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
return false;
}
/// InsertBranch - Insert a branch into the end of the specified
/// MachineBasicBlock. This operands to this method are the same as those
/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch

4
lib/Target/PIC16/PIC16InstrInfo.h
View File

@ -61,10 +61,6 @@ public:
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
virtual
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,

61
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -39,67 +39,6 @@ PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
RI(*TM.getSubtargetImpl(), *this) {}
bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg,
unsigned& sourceSubIdx,
unsigned& destSubIdx) const {
sourceSubIdx = destSubIdx = 0; // No sub-registers.
unsigned oc = MI.getOpcode();
if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
MI.getOperand(2).isReg() &&
"invalid PPC OR instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::ADDI) { // addi r1, r2, 0
assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isReg() &&
MI.getOperand(2).isImm() &&
"invalid PPC ADDI instruction!");
if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::ORI) { // ori r1, r2, 0
assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
MI.getOperand(2).isImm() &&
"invalid PPC ORI instruction!");
if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::FMR) { // fmr r1, r2
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid PPC FMR instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid PPC MCRF instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
return false;
}
unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {

6
lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -82,12 +82,6 @@ public:
///
virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,

40
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -28,46 +28,6 @@ SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
RI(ST, *this), Subtarget(ST) {
}
static bool isZeroImm(const MachineOperand &op) {
return op.isImm() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSR, unsigned &DstSR) const {
SrcSR = DstSR = 0; // No sub-registers.
// We look for 3 kinds of patterns here:
// or with G0 or 0
// add with G0 or 0
// fmovs or FpMOVD (pseudo double move).
if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
if (MI.getOperand(1).getReg() == SP::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (MI.getOperand(2).getReg() == SP::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
} else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
} else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
MI.getOpcode() == SP::FMOVD) {
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
}
return false;
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

6
lib/Target/Sparc/SparcInstrInfo.h
View File

@ -43,12 +43,6 @@ public:
///
virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

25
lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -141,31 +141,6 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc));
}
bool
SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
switch (MI.getOpcode()) {
default:
return false;
case SystemZ::MOV32rr:
case SystemZ::MOV64rr:
case SystemZ::MOV64rrP:
case SystemZ::MOV128rr:
case SystemZ::FMOV32rr:
case SystemZ::FMOV64rr:
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid register-register move instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
SrcSubIdx = MI.getOperand(1).getSubReg();
DstSubIdx = MI.getOperand(0).getSubReg();
return true;
}
}
unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {

3
lib/Target/SystemZ/SystemZInstrInfo.h
View File

@ -65,9 +65,6 @@ public:
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
bool isMoveInstr(const MachineInstr& MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;

40
lib/Target/X86/X86InstrInfo.cpp
View File

@ -667,46 +667,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
}
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
switch (MI.getOpcode()) {
default:
return false;
case X86::MOV8rr:
case X86::MOV8rr_NOREX:
case X86::MOV16rr:
case X86::MOV32rr:
case X86::MOV64rr:
case X86::MOV32rr_TC:
case X86::MOV64rr_TC:
// FP Stack register class copies
case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
case X86::MOV_Fp3264: case X86::MOV_Fp3280:
case X86::MOV_Fp6432: case X86::MOV_Fp8032:
// Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
// copies are done with FsMOVAPSrr and FsMOVAPDrr.
case X86::FsMOVAPSrr:
case X86::FsMOVAPDrr:
case X86::MOVAPSrr:
case X86::MOVAPDrr:
case X86::MOVDQArr:
case X86::MMX_MOVQ64rr:
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"invalid register-register move instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
SrcSubIdx = MI.getOperand(1).getSubReg();
DstSubIdx = MI.getOperand(0).getSubReg();
return true;
}
}
bool
X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,

6
lib/Target/X86/X86InstrInfo.h
View File

@ -610,12 +610,6 @@ public:
///
virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
/// extension instruction. That is, it's like a copy where it's legal for the
/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns

27
lib/Target/XCore/XCoreInstrInfo.cpp
View File

@ -46,33 +46,6 @@ static bool isZeroImm(const MachineOperand &op) {
return op.isImm() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSR, unsigned &DstSR) const {
SrcSR = DstSR = 0; // No sub-registers.
// We look for 4 kinds of patterns here:
// add dst, src, 0
// sub dst, src, 0
// or dst, src, src
// and dst, src, src
if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus)
&& isZeroImm(MI.getOperand(2))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
} else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r)
&& MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
return false;
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If

6
lib/Target/XCore/XCoreInstrInfo.h
View File

@ -30,12 +30,6 @@ public:
///
virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If