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X86FastISel support for double->float and float->double casts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56070 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -92,6 +92,9 @@ private:
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bool X86SelectTrunc(Instruction *I);
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bool X86SelectFPExt(Instruction *I);
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bool X86SelectFPTrunc(Instruction *I);
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bool X86SelectCall(Instruction *I);
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CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
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@ -656,6 +659,42 @@ bool X86FastISel::X86SelectSelect(Instruction *I) {
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return true;
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}
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bool X86FastISel::X86SelectFPExt(Instruction *I) {
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if (Subtarget->hasSSE2()) {
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if (I->getType() == Type::DoubleTy) {
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Value *V = I->getOperand(0);
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if (V->getType() == Type::FloatTy) {
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unsigned OpReg = getRegForValue(V);
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if (OpReg == 0) return false;
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unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
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BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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}
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return false;
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}
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bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
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if (Subtarget->hasSSE2()) {
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if (I->getType() == Type::FloatTy) {
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Value *V = I->getOperand(0);
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if (V->getType() == Type::DoubleTy) {
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unsigned OpReg = getRegForValue(V);
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if (OpReg == 0) return false;
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unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
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BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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}
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return false;
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}
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bool X86FastISel::X86SelectTrunc(Instruction *I) {
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if (Subtarget->is64Bit())
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// All other cases should be handled by the tblgen generated code.
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@ -937,6 +976,10 @@ X86FastISel::TargetSelectInstruction(Instruction *I) {
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return X86SelectSelect(I);
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case Instruction::Trunc:
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return X86SelectTrunc(I);
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case Instruction::FPExt:
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return X86SelectFPExt(I);
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case Instruction::FPTrunc:
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return X86SelectFPTrunc(I);
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}
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return false;
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