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[mips][microMIPS] Implement SWP and LWP instructions
Differential Revision: http://reviews.llvm.org/D5667 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -146,6 +146,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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MipsAsmParser::OperandMatchResultTy parseLSAImm(OperandVector &Operands);
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MipsAsmParser::OperandMatchResultTy parseLSAImm(OperandVector &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseRegisterPair (OperandVector &Operands);
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::OperandMatchResultTy
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parseRegisterList (OperandVector &Operands);
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parseRegisterList (OperandVector &Operands);
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@ -428,7 +431,8 @@ private:
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k_PhysRegister, /// A physical register from the Mips namespace
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k_PhysRegister, /// A physical register from the Mips namespace
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k_RegisterIndex, /// A register index in one or more RegKind.
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k_RegisterIndex, /// A register index in one or more RegKind.
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k_Token, /// A simple token
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k_Token, /// A simple token
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k_RegList /// A physical register list
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k_RegList, /// A physical register list
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k_RegPair /// A pair of physical register
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} Kind;
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} Kind;
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public:
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public:
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@ -781,6 +785,13 @@ public:
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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}
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}
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void addRegPairOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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unsigned RegNo = getRegPair();
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Inst.addOperand(MCOperand::CreateReg(RegNo++));
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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}
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bool isReg() const override {
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bool isReg() const override {
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// As a special case until we sort out the definition of div/divu, pretend
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// As a special case until we sort out the definition of div/divu, pretend
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// that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
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// that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
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@ -845,6 +856,7 @@ public:
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assert(Kind == k_Token && "Invalid access!");
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assert(Kind == k_Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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return StringRef(Tok.Data, Tok.Length);
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}
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}
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bool isRegPair() const { return Kind == k_RegPair; }
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unsigned getReg() const override {
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unsigned getReg() const override {
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// As a special case until we sort out the definition of div/divu, pretend
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// As a special case until we sort out the definition of div/divu, pretend
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@ -886,6 +898,11 @@ public:
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return *(RegList.List);
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return *(RegList.List);
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}
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}
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unsigned getRegPair() const {
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assert((Kind == k_RegPair) && "Invalid access!");
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return RegIdx.Index;
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}
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static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
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static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
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MipsAsmParser &Parser) {
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MipsAsmParser &Parser) {
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auto Op = make_unique<MipsOperand>(k_Token, Parser);
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auto Op = make_unique<MipsOperand>(k_Token, Parser);
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@ -995,6 +1012,15 @@ public:
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return Op;
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return Op;
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}
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}
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static std::unique_ptr<MipsOperand>
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CreateRegPair(unsigned RegNo, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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auto Op = make_unique<MipsOperand>(k_RegPair, Parser);
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Op->RegIdx.Index = RegNo;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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bool isGPRAsmReg() const {
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bool isGPRAsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
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return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
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}
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}
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@ -1061,6 +1087,7 @@ public:
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case k_PhysRegister:
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case k_PhysRegister:
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case k_RegisterIndex:
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case k_RegisterIndex:
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case k_Token:
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case k_Token:
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case k_RegPair:
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break;
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break;
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}
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}
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}
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}
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@ -1094,6 +1121,9 @@ public:
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OS << Reg << " ";
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OS << Reg << " ";
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OS << ">";
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OS << ">";
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break;
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break;
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case k_RegPair:
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OS << "RegPair<" << RegIdx.Index << "," << RegIdx.Index + 1 << ">";
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break;
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}
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}
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}
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}
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}; // class MipsOperand
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}; // class MipsOperand
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@ -2723,6 +2753,22 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) {
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return MatchOperand_Success;
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return MatchOperand_Success;
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}
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseRegisterPair(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = Parser.getTok().getLoc();
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if (parseAnyRegister(Operands) != MatchOperand_Success)
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return MatchOperand_ParseFail;
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SMLoc E = Parser.getTok().getLoc();
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MipsOperand &Op = static_cast<MipsOperand &>(*Operands.back());
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unsigned Reg = Op.getGPR32Reg();
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Operands.pop_back();
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Operands.push_back(MipsOperand::CreateRegPair(Reg, S, E, *this));
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return MatchOperand_Success;
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}
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MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
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MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
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MCSymbolRefExpr::VariantKind VK =
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MCSymbolRefExpr::VariantKind VK =
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@ -1222,6 +1222,9 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
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// fallthrough
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// fallthrough
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default:
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default:
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Reg));
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if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
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Inst.addOperand(MCOperand::CreateReg(Reg+1));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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}
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}
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@ -261,6 +261,11 @@ printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
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O << MipsFCCToString((Mips::CondCode)MO.getImm());
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O << MipsFCCToString((Mips::CondCode)MO.getImm());
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}
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}
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void MipsInstPrinter::
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printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) {
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printRegName(O, MI->getOperand(opNum).getReg());
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}
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void MipsInstPrinter::
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void MipsInstPrinter::
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printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
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printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
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llvm_unreachable("TODO");
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llvm_unreachable("TODO");
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@ -99,6 +99,7 @@ private:
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void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
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void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
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void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
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void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
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void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
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void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
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void printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O);
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void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
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void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
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bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
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bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
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@ -862,4 +862,11 @@ MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
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return (MI.getNumOperands() - 4);
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return (MI.getNumOperands() - 4);
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}
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}
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unsigned
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MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
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}
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#include "MipsGenMCCodeEmitter.inc"
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#include "MipsGenMCCodeEmitter.inc"
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@ -184,6 +184,10 @@ public:
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SmallVectorImpl<MCFixup> &Fixups,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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const MCSubtargetInfo &STI) const;
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unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
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unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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const MCSubtargetInfo &STI) const;
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@ -148,6 +148,36 @@ class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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let DecoderMethod = "DecodeMemMMImm12";
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let DecoderMethod = "DecodeMemMMImm12";
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}
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}
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/// A register pair used by load/store pair instructions.
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def RegPairAsmOperand : AsmOperandClass {
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let Name = "RegPair";
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let ParserMethod = "parseRegisterPair";
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}
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def regpair : Operand<i32> {
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let EncoderMethod = "getRegisterPairOpValue";
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let ParserMatchClass = RegPairAsmOperand;
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let PrintMethod = "printRegisterPair";
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let DecoderMethod = "DecodeRegPairOperand";
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let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
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}
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class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
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ComplexPattern Addr = addr> :
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InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayStore = 1;
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}
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class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
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ComplexPattern Addr = addr> :
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InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayLoad = 1;
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}
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class LLBaseMM<string opstr, RegisterOperand RO> :
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class LLBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
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InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
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!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
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@ -555,6 +585,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
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def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
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def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
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def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
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/// Load and Store Pair Instructions
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def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
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def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
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/// Move Conditional
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/// Move Conditional
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def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
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def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM_MM<0, 0x58>;
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NoItinerary>, ADD_FM_MM<0, 0x58>;
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@ -343,6 +343,12 @@
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# CHECK: swm32 $16, $17, 8($4)
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# CHECK: swm32 $16, $17, 8($4)
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0x20 0x44 0xd0 0x08
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0x20 0x44 0xd0 0x08
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# CHECK: swp $16, 8($4)
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0x22 0x04 0x90 0x08
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# CHECK: lwp $16, 8($4)
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0x22 0x04 0x10 0x08
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# CHECK: nop
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# CHECK: nop
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0x00 0x00 0x00 0x00
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0x00 0x00 0x00 0x00
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# CHECK: swm32 $16, $17, 8($4)
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# CHECK: swm32 $16, $17, 8($4)
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0x44 0x20 0x08 0xd0
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0x44 0x20 0x08 0xd0
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# CHECK: swp $16, 8($4)
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0x04 0x22 0x08 0x90
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# CHECK: lwp $16, 8($4)
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0x04 0x22 0x08 0x10
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# CHECK: nop
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# CHECK: nop
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0x00 0x00 0x00 0x00
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0x00 0x00 0x00 0x00
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# CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0]
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# CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0]
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# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
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# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
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# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
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# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
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# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90]
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# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# Big endian
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# Big endian
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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@ -56,6 +58,8 @@
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# CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
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# CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
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# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
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# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
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# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
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# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
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# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
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# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
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lb $5, 8($4)
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lb $5, 8($4)
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lbu $6, 8($4)
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lbu $6, 8($4)
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lh $2, 8($4)
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lh $2, 8($4)
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@ -78,3 +82,5 @@
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swm32 $16 - $19, 8($4)
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swm32 $16 - $19, 8($4)
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lwm16 $16, $17, $ra, 8($sp)
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lwm16 $16, $17, $ra, 8($sp)
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swm16 $16, $17, $ra, 8($sp)
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swm16 $16, $17, $ra, 8($sp)
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swp $16, 8($4)
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lwp $16, 8($4)
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