mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-04 16:01:46 +00:00
[ARM] generate VMAXNM/VMINNM for a compare followed by a select, in safe math mode too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236590 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov
parent
5fa37a7f2d
commit
78fc2103c9
@ -3377,12 +3377,6 @@ SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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SelectTrue, SelectFalse, ISD::SETNE);
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}
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static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
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if (CC == ISD::SETNE)
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return ISD::SETEQ;
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return ISD::getSetCCInverse(CC, true);
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}
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static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
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bool &swpCmpOps, bool &swpVselOps) {
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// Start by selecting the GE condition code for opcodes that return true for
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@ -3495,7 +3489,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
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if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
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CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
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CC = getInverseCCForVSEL(CC);
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CC = ISD::getSetCCInverse(CC, true);
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std::swap(TrueVal, FalseVal);
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}
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}
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@ -3517,27 +3511,108 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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// c = fcmp [?gt, ?ge, ?lt, ?le] a, b
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// select c, a, b
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// In NoNaNsFPMath the CC will have been changed from, e.g., 'ogt' to 'gt'.
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// We only do this transformation in UnsafeFPMath and for no-NaNs
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// comparisons, because signed zeros and NaNs are handled differently than
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// the original code sequence.
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// FIXME: There are more cases that can be transformed even with NaNs,
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// signed zeroes and safe math. E.g. in the following, the result will be
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// FalseVal if a is a NaN or -0./0. and that's what vmaxnm will give, too.
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// c = fcmp ogt, a, 0. ; select c, a, 0. => vmaxnm a, 0.
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// FIXME: There is similar code that allows some extensions in
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// AArch64TargetLowering::LowerSELECT_CC that should be shared with this
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// code.
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if (getTargetMachine().Options.UnsafeFPMath) {
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if (LHS == TrueVal && RHS == FalseVal) {
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if (CC == ISD::SETGT || CC == ISD::SETGE)
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return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
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if (CC == ISD::SETLT || CC == ISD::SETLE)
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return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
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} else if (LHS == FalseVal && RHS == TrueVal) {
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if (CC == ISD::SETLT || CC == ISD::SETLE)
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return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
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if (CC == ISD::SETGT || CC == ISD::SETGE)
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return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
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bool swapSides = false;
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if (!getTargetMachine().Options.NoNaNsFPMath) {
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// transformability may depend on which way around we compare
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switch (CC) {
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default:
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break;
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case ISD::SETOGT:
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case ISD::SETOGE:
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case ISD::SETOLT:
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case ISD::SETOLE:
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// the non-NaN should be RHS
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swapSides = DAG.isKnownNeverNaN(LHS) && !DAG.isKnownNeverNaN(RHS);
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break;
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETULT:
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case ISD::SETULE:
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// the non-NaN should be LHS
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swapSides = DAG.isKnownNeverNaN(RHS) && !DAG.isKnownNeverNaN(LHS);
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break;
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}
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}
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swapSides = swapSides || (LHS == FalseVal && RHS == TrueVal);
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if (swapSides) {
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CC = ISD::getSetCCSwappedOperands(CC);
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std::swap(LHS, RHS);
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}
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if (LHS == TrueVal && RHS == FalseVal) {
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bool canTransform = true;
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// FIXME: FastMathFlags::noSignedZeros() doesn't appear reachable from here
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if (!getTargetMachine().Options.UnsafeFPMath &&
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!DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
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const ConstantFPSDNode *Zero;
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switch (CC) {
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default:
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break;
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case ISD::SETOGT:
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case ISD::SETUGT:
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case ISD::SETGT:
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// RHS must not be -0
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canTransform = (Zero = dyn_cast<ConstantFPSDNode>(RHS)) &&
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!Zero->isNegative();
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break;
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case ISD::SETOGE:
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case ISD::SETUGE:
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case ISD::SETGE:
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// LHS must not be -0
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canTransform = (Zero = dyn_cast<ConstantFPSDNode>(LHS)) &&
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!Zero->isNegative();
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break;
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case ISD::SETOLT:
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case ISD::SETULT:
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case ISD::SETLT:
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// RHS must not be +0
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canTransform = (Zero = dyn_cast<ConstantFPSDNode>(RHS)) &&
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Zero->isNegative();
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break;
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case ISD::SETOLE:
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case ISD::SETULE:
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case ISD::SETLE:
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// LHS must not be +0
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canTransform = (Zero = dyn_cast<ConstantFPSDNode>(LHS)) &&
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Zero->isNegative();
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break;
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}
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}
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if (canTransform) {
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// Note: If one of the elements in a pair is a number and the other
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// element is NaN, the corresponding result element is the number.
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// This is consistent with the IEEE 754-2008 standard.
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// Therefore, a > b ? a : b <=> vmax(a,b), if b is constant and a is NaN
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switch (CC) {
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default:
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break;
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case ISD::SETOGT:
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case ISD::SETOGE:
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if (!DAG.isKnownNeverNaN(RHS))
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break;
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return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
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case ISD::SETUGT:
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case ISD::SETUGE:
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if (!DAG.isKnownNeverNaN(LHS))
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break;
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case ISD::SETGT:
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case ISD::SETGE:
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return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
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case ISD::SETOLT:
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case ISD::SETOLE:
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if (!DAG.isKnownNeverNaN(RHS))
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break;
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return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
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case ISD::SETULT:
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case ISD::SETULE:
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if (!DAG.isKnownNeverNaN(LHS))
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break;
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case ISD::SETLT:
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case ISD::SETLE:
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return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
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}
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}
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}
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@ -218,6 +218,291 @@ define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) {
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ret double %cond
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}
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; known non-NaNs
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define float @fp-armv8_vminnm_NNNo(float %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo":
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; CHECK-FAST: vminnm.f32
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_NNNo":
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; CHECK: vminnm.f32
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; CHECK-NOT: vminnm.f32
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%cmp1 = fcmp olt float %a, 12.
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%cond1 = select i1 %cmp1, float %a, float 12.
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%cmp2 = fcmp olt float 34., %cond1
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%cond2 = select i1 %cmp2, float 34., float %cond1
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ret float %cond2
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}
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define double @fp-armv8_vminnm_NNNole(double %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNole":
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; CHECK-FAST: vminnm.f64
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; CHECK-FAST: vminnm.f64
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; CHECK-LABEL: "fp-armv8_vminnm_NNNole":
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; CHECK: vminnm.f64
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; CHECK-NOT: vminnm.f64
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%cmp1 = fcmp ole double %a, 34.
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%cond1 = select i1 %cmp1, double %a, double 34.
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%cmp2 = fcmp ole double 56., %cond1
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%cond2 = select i1 %cmp2, double 56., double %cond1
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ret double %cond2
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}
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define float @fp-armv8_vminnm_NNNo_rev(float %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo_rev":
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; CHECK-FAST: vminnm.f32
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev":
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; CHECK: vminnm.f32
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; CHECK-NOT: vminnm.f32
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%cmp1 = fcmp ogt float %a, 56.
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%cond1 = select i1 %cmp1, float 56., float %a
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%cmp2 = fcmp ogt float 78., %cond1
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%cond2 = select i1 %cmp2, float %cond1, float 78.
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ret float %cond2
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}
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define double @fp-armv8_vminnm_NNNoge_rev(double %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNoge_rev":
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; CHECK-FAST: vminnm.f64
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; CHECK-FAST: vminnm.f64
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; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev":
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; CHECK: vminnm.f64
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; CHECK-NOT: vminnm.f64
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%cmp1 = fcmp oge double %a, 78.
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%cond1 = select i1 %cmp1, double 78., double %a
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%cmp2 = fcmp oge double 90., %cond1
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%cond2 = select i1 %cmp2, double %cond1, double 90.
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ret double %cond2
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}
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define float @fp-armv8_vminnm_NNNu(float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu":
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; CHECK-FAST: vminnm.f32
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_NNNu":
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; CHECK: vminnm.f32
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; CHECK-NOT: vminnm.f32
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%cmp1 = fcmp ult float 12., %b
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%cond1 = select i1 %cmp1, float 12., float %b
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%cmp2 = fcmp ult float %cond1, 34.
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%cond2 = select i1 %cmp2, float %cond1, float 34.
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ret float %cond2
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}
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define float @fp-armv8_vminnm_NNNule(float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNule":
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; CHECK-FAST: vminnm.f32
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_NNNule":
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; CHECK: vminnm.f32
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; CHECK-NOT: vminnm.f32
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%cmp1 = fcmp ule float 34., %b
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%cond1 = select i1 %cmp1, float 34., float %b
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%cmp2 = fcmp ule float %cond1, 56.
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%cond2 = select i1 %cmp2, float %cond1, float 56.
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ret float %cond2
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}
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define float @fp-armv8_vminnm_NNNu_rev(float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu_rev":
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; CHECK-FAST: vminnm.f32
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev":
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; CHECK: vminnm.f32
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; CHECK-NOT: vminnm.f32
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%cmp1 = fcmp ugt float 56., %b
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%cond1 = select i1 %cmp1, float %b, float 56.
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%cmp2 = fcmp ugt float %cond1, 78.
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%cond2 = select i1 %cmp2, float 78., float %cond1
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ret float %cond2
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}
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define double @fp-armv8_vminnm_NNNuge_rev(double %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNuge_rev":
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; CHECK-FAST: vminnm.f64
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; CHECK-FAST: vminnm.f64
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; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev":
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; CHECK: vminnm.f64
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; CHECK-NOT: vminnm.f64
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%cmp1 = fcmp uge double 78., %b
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%cond1 = select i1 %cmp1, double %b, double 78.
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%cmp2 = fcmp uge double %cond1, 90.
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%cond2 = select i1 %cmp2, double 90., double %cond1
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ret double %cond2
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}
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define float @fp-armv8_vmaxnm_NNNo(float %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo":
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; CHECK-FAST: vmaxnm.f32
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo":
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; CHECK: vmaxnm.f32
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; CHECK-NOT: vmaxnm.f32
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%cmp1 = fcmp ogt float %a, 12.
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%cond1 = select i1 %cmp1, float %a, float 12.
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%cmp2 = fcmp ogt float 34., %cond1
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%cond2 = select i1 %cmp2, float 34., float %cond1
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNoge(float %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNoge":
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; CHECK-FAST: vmaxnm.f32
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNoge":
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; CHECK: vmaxnm.f32
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; CHECK-NOT: vmaxnm.f32
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%cmp1 = fcmp oge float %a, 34.
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%cond1 = select i1 %cmp1, float %a, float 34.
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%cmp2 = fcmp oge float 56., %cond1
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%cond2 = select i1 %cmp2, float 56., float %cond1
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNo_rev(float %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo_rev":
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; CHECK-FAST: vmaxnm.f32
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo_rev":
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; CHECK: vmaxnm.f32
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; CHECK-NOT: vmaxnm.f32
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%cmp1 = fcmp olt float %a, 56.
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%cond1 = select i1 %cmp1, float 56., float %a
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%cmp2 = fcmp olt float 78., %cond1
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%cond2 = select i1 %cmp2, float %cond1, float 78.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNole_rev(float %a) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNole_rev":
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; CHECK-FAST: vmaxnm.f32
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNole_rev":
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; CHECK: vmaxnm.f32
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; CHECK-NOT: vmaxnm.f32
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%cmp1 = fcmp ole float %a, 78.
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%cond1 = select i1 %cmp1, float 78., float %a
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%cmp2 = fcmp ole float 90., %cond1
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%cond2 = select i1 %cmp2, float %cond1, float 90.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNu(float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu":
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; CHECK-FAST: vmaxnm.f32
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu":
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; CHECK: vmaxnm.f32
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; CHEC-NOT: vmaxnm.f32
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%cmp1 = fcmp ugt float 12., %b
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%cond1 = select i1 %cmp1, float 12., float %b
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%cmp2 = fcmp ugt float %cond1, 34.
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%cond2 = select i1 %cmp2, float %cond1, float 34.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNuge(float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNuge":
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; CHECK-FAST: vmaxnm.f32
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNuge":
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; CHECK: vmaxnm.f32
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; CHECK-NOT: vmaxnm.f32
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%cmp1 = fcmp uge float 34., %b
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%cond1 = select i1 %cmp1, float 34., float %b
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%cmp2 = fcmp uge float %cond1, 56.
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%cond2 = select i1 %cmp2, float %cond1, float 56.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNu_rev(float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu_rev":
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; CHECK-FAST: vmaxnm.f32
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu_rev":
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; CHECK: vmaxnm.f32
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; CHECK-NOT: vmaxnm.f32
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%cmp1 = fcmp ult float 56., %b
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%cond1 = select i1 %cmp1, float %b, float 56.
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%cmp2 = fcmp ult float %cond1, 78.
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%cond2 = select i1 %cmp2, float 78., float %cond1
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ret float %cond2
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}
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define double @fp-armv8_vmaxnm_NNNule_rev( double %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNule_rev":
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; CHECK-FAST: vmaxnm.f64
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; CHECK-FAST: vmaxnm.f64
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNule_rev":
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; CHECK: vmaxnm.f64
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; CHECK-NOT: vmaxnm.f64
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%cmp1 = fcmp ule double 78., %b
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%cond1 = select i1 %cmp1, double %b, double 78.
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%cmp2 = fcmp ule double %cond1, 90.
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%cond2 = select i1 %cmp2, double 90., double %cond1
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ret double %cond2
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}
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define float @fp-armv8_vminmaxnm_0(float %a) {
|
||||
; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_0":
|
||||
; CHECK-FAST-NOT: vcmp
|
||||
; CHECK-FAST: vminnm.f32
|
||||
; CHECK-FAST: vmaxnm.f32
|
||||
; CHECK-LABEL: "fp-armv8_vminmaxnm_0":
|
||||
; CHECK-NOT: vminnm.f32
|
||||
; CHECK: vmaxnm.f32
|
||||
%cmp1 = fcmp olt float %a, 0.
|
||||
%cond1 = select i1 %cmp1, float %a, float 0.
|
||||
%cmp2 = fcmp ogt float %cond1, 0.
|
||||
%cond2 = select i1 %cmp2, float %cond1, float 0.
|
||||
ret float %cond2
|
||||
}
|
||||
|
||||
define float @fp-armv8_vminmaxnm_neg0(float %a) {
|
||||
; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_neg0":
|
||||
; CHECK-FAST-NOT: vcmp
|
||||
; CHECK-FAST: vminnm.f32
|
||||
; CHECK-FAST: vmaxnm.f32
|
||||
; CHECK-LABEL: "fp-armv8_vminmaxnm_neg0":
|
||||
; CHECK: vminnm.f32
|
||||
; CHECK-NOT: vmaxnm.f32
|
||||
%cmp1 = fcmp olt float %a, -0.
|
||||
%cond1 = select i1 %cmp1, float %a, float -0.
|
||||
%cmp2 = fcmp ogt float %cond1, -0.
|
||||
%cond2 = select i1 %cmp2, float %cond1, float -0.
|
||||
ret float %cond2
|
||||
}
|
||||
|
||||
define float @fp-armv8_vminmaxnm_e_0(float %a) {
|
||||
; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_0":
|
||||
; CHECK-FAST-NOT: vcmp
|
||||
; CHECK-FAST: vminnm.f32
|
||||
; CHECK-FAST: vmaxnm.f32
|
||||
; CHECK-LABEL: "fp-armv8_vminmaxnm_e_0":
|
||||
; CHECK-NOT: vminnm.f32
|
||||
; CHECK: vmaxnm.f32
|
||||
%cmp1 = fcmp ule float 0., %a
|
||||
%cond1 = select i1 %cmp1, float 0., float %a
|
||||
%cmp2 = fcmp uge float 0., %cond1
|
||||
%cond2 = select i1 %cmp2, float 0., float %cond1
|
||||
ret float %cond2
|
||||
}
|
||||
|
||||
define float @fp-armv8_vminmaxnm_e_neg0(float %a) {
|
||||
; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_neg0":
|
||||
; CHECK-FAST-NOT: vcmp
|
||||
; CHECK-FAST: vminnm.f32
|
||||
; CHECK-FAST: vmaxnm.f32
|
||||
; CHECK-LABEL: "fp-armv8_vminmaxnm_e_neg0":
|
||||
; CHECK: vminnm.f32
|
||||
; CHECK-NOT: vmaxnm.f32
|
||||
%cmp1 = fcmp ule float -0., %a
|
||||
%cond1 = select i1 %cmp1, float -0., float %a
|
||||
%cmp2 = fcmp uge float -0., %cond1
|
||||
%cond2 = select i1 %cmp2, float -0., float %cond1
|
||||
ret float %cond2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
||||
declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
||||
|
||||
Loading…
Reference in New Issue
Block a user