From 792016bc2202d34d0a3d0b5d12985eca5528c24c Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Fri, 23 Sep 2011 18:28:39 +0000 Subject: [PATCH] Make FGR64RegisterClass available if target is Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index fbd2f4b8460..0c0b9abdd3f 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -84,6 +84,7 @@ MipsTargetLowering:: MipsTargetLowering(MipsTargetMachine &TM) : TargetLowering(TM, new MipsTargetObjectFile()) { Subtarget = &TM.getSubtarget(); + bool HasMips64 = Subtarget->hasMips64(); // Mips does not have i1 type, so use i32 for // setcc operations results (slt, sgt, ...). @@ -95,8 +96,12 @@ MipsTargetLowering(MipsTargetMachine &TM) addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); // When dealing with single precision only, use libcalls - if (!Subtarget->isSingleFloat()) + if (!Subtarget->isSingleFloat()) { + if (HasMips64) + addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); + else addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); + } // Load extented operations for i1 types must be promoted setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);