From 793ce99ea79b2a51a9ace18adcae60678efaae9e Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 31 Oct 2013 12:14:17 +0000 Subject: [PATCH] [SystemZ] Automatically detect zEC12 and z196 hosts As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 42 +++++++++++++++++++++ lib/Target/SystemZ/SystemZProcessors.td | 5 ++- lib/Target/SystemZ/SystemZSubtarget.cpp | 7 +++- test/CodeGen/SystemZ/atomicrmw-minmax-03.ll | 5 ++- test/CodeGen/SystemZ/atomicrmw-minmax-04.ll | 5 ++- test/CodeGen/SystemZ/cond-store-01.ll | 5 ++- test/CodeGen/SystemZ/cond-store-02.ll | 5 ++- test/CodeGen/SystemZ/fp-cmp-01.ll | 5 ++- test/CodeGen/SystemZ/fp-cmp-02.ll | 5 ++- test/CodeGen/SystemZ/fp-cmp-03.ll | 5 ++- test/CodeGen/SystemZ/fp-move-02.ll | 5 ++- test/CodeGen/SystemZ/frame-13.ll | 9 +++-- test/CodeGen/SystemZ/frame-14.ll | 10 +++-- test/CodeGen/SystemZ/frame-15.ll | 9 +++-- test/CodeGen/SystemZ/frame-16.ll | 8 +++- test/CodeGen/SystemZ/frame-18.ll | 5 ++- test/CodeGen/SystemZ/int-add-11.ll | 5 ++- test/CodeGen/SystemZ/int-conv-02.ll | 5 ++- test/CodeGen/SystemZ/int-conv-06.ll | 5 ++- test/CodeGen/SystemZ/risbg-01.ll | 3 +- test/CodeGen/SystemZ/setcc-01.ll | 5 ++- test/CodeGen/SystemZ/setcc-02.ll | 5 ++- test/CodeGen/SystemZ/spill-01.ll | 5 ++- 23 files changed, 123 insertions(+), 45 deletions(-) diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index 12df08c6c0c..6a5d4d28a91 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -535,6 +535,48 @@ std::string sys::getHostCPUName() { return "generic"; } +#elif defined(__linux__) && defined(__s390x__) +std::string sys::getHostCPUName() { + // STIDP is a privileged operation, so use /proc/cpuinfo instead. + // Note: We cannot mmap /proc/cpuinfo here and then process the resulting + // memory buffer because the 'file' has 0 size (it can be read from only + // as a stream). + + std::string Err; + DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err); + if (!DS) { + DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n"); + return "generic"; + } + + // The "processor 0:" line comes after a fair amount of other information, + // including a cache breakdown, but this should be plenty. + char buffer[2048]; + size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer)); + delete DS; + + StringRef Str(buffer, CPUInfoSize); + SmallVector Lines; + Str.split(Lines, "\n"); + for (unsigned I = 0, E = Lines.size(); I != E; ++I) { + if (Lines[I].startswith("processor ")) { + size_t Pos = Lines[I].find("machine = "); + if (Pos != StringRef::npos) { + Pos += sizeof("machine = ") - 1; + unsigned int Id; + if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { + if (Id >= 2827) + return "zEC12"; + if (Id >= 2817) + return "z196"; + } + } + break; + } + } + + return "generic"; +} #else std::string sys::getHostCPUName() { return "generic"; diff --git a/lib/Target/SystemZ/SystemZProcessors.td b/lib/Target/SystemZ/SystemZProcessors.td index 00d4338af55..f241fb0c222 100644 --- a/lib/Target/SystemZ/SystemZProcessors.td +++ b/lib/Target/SystemZ/SystemZProcessors.td @@ -36,8 +36,9 @@ def FeatureFPExtension : SystemZFeature< "Assume that the floating-point extension facility is installed" >; -def : Processor<"z10", NoItineraries, []>; -def : Processor<"z196", NoItineraries, +def : Processor<"generic", NoItineraries, []>; +def : Processor<"z10", NoItineraries, []>; +def : Processor<"z196", NoItineraries, [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, FeatureFPExtension]>; def : Processor<"zEC12", NoItineraries, diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp index b6a63923cf5..474192099f2 100644 --- a/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -9,6 +9,7 @@ #include "SystemZSubtarget.h" #include "llvm/IR/GlobalValue.h" +#include "llvm/Support/Host.h" #include "MCTargetDesc/SystemZMCTargetDesc.h" #define GET_SUBTARGETINFO_TARGET_DESC @@ -25,7 +26,11 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT, TargetTriple(TT) { std::string CPUName = CPU; if (CPUName.empty()) - CPUName = "z10"; + CPUName = "generic"; +#if defined(__linux__) && defined(__s390x__) + if (CPUName == "generic") + CPUName = sys::getHostCPUName(); +#endif // Parse features string. ParseSubtargetFeatures(CPUName, FS); diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll index 418f156b24a..f2152c6f28b 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll @@ -1,6 +1,7 @@ -; Test 32-bit atomic minimum and maximum. +; Test 32-bit atomic minimum and maximum. Here we match the z10 versions, +; which can't use LOCR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check signed minium. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll index 9d26d28bc1d..037eb1aa936 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll @@ -1,6 +1,7 @@ -; Test 64-bit atomic minimum and maximum. +; Test 64-bit atomic minimum and maximum. Here we match the z10 versions, +; which can't use LOCGR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check signed minium. define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll index 5b559340198..d55ea2133e8 100644 --- a/test/CodeGen/SystemZ/cond-store-01.ll +++ b/test/CodeGen/SystemZ/cond-store-01.ll @@ -1,6 +1,7 @@ -; Test 8-bit conditional stores that are presented as selects. +; Test 8-bit conditional stores that are presented as selects. The volatile +; tests require z10, which use a branch instead of a LOCR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s declare void @foo(i8 *) diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll index 9e188437a5f..91bc4860b38 100644 --- a/test/CodeGen/SystemZ/cond-store-02.ll +++ b/test/CodeGen/SystemZ/cond-store-02.ll @@ -1,6 +1,7 @@ -; Test 16-bit conditional stores that are presented as selects. +; Test 16-bit conditional stores that are presented as selects. The volatile +; tests require z10, which use a branch instead of a LOCR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s declare void @foo(i16 *) diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll index 7f194014f92..d7c0cce9c2a 100644 --- a/test/CodeGen/SystemZ/fp-cmp-01.ll +++ b/test/CodeGen/SystemZ/fp-cmp-01.ll @@ -1,6 +1,7 @@ -; Test 32-bit floating-point comparison. +; Test 32-bit floating-point comparison. The tests assume a z10 implementation +; of select, using conditional branches rather than LOCGR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s declare float @foo() diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll index 1cd6da8c770..c61f04ed244 100644 --- a/test/CodeGen/SystemZ/fp-cmp-02.ll +++ b/test/CodeGen/SystemZ/fp-cmp-02.ll @@ -1,6 +1,7 @@ -; Test 64-bit floating-point comparison. +; Test 64-bit floating-point comparison. The tests assume a z10 implementation +; of select, using conditional branches rather than LOCGR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s declare double @foo() diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll index 0f71f4e3a92..e777d00c968 100644 --- a/test/CodeGen/SystemZ/fp-cmp-03.ll +++ b/test/CodeGen/SystemZ/fp-cmp-03.ll @@ -1,6 +1,7 @@ -; Test 128-bit floating-point comparison. +; Test 128-bit floating-point comparison. The tests assume a z10 implementation +; of select, using conditional branches rather than LOCGR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; There is no memory form of 128-bit comparison. define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) { diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll index 6f9da9ab69d..505ee8d37a4 100644 --- a/test/CodeGen/SystemZ/fp-move-02.ll +++ b/test/CodeGen/SystemZ/fp-move-02.ll @@ -1,6 +1,7 @@ -; Test moves between FPRs and GPRs. +; Test moves between FPRs and GPRs. The 32-bit cases test the z10 +; implementation, which has no high-word support. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s declare i64 @foo() declare double @bar() diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll index 60bff508d93..393850fbf61 100644 --- a/test/CodeGen/SystemZ/frame-13.ll +++ b/test/CodeGen/SystemZ/frame-13.ll @@ -1,8 +1,11 @@ ; Test the handling of base + 12-bit displacement addresses for large frames, -; in cases where no 20-bit form exists. +; in cases where no 20-bit form exists. The tests here assume z10 register +; pressure, without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \ +; RUN: FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \ +; RUN: FileCheck -check-prefix=CHECK-FP %s ; This file tests what happens when a displacement is converted from ; being relative to the start of a frame object to being relative to diff --git a/test/CodeGen/SystemZ/frame-14.ll b/test/CodeGen/SystemZ/frame-14.ll index 22a45eecf30..3b48179c40b 100644 --- a/test/CodeGen/SystemZ/frame-14.ll +++ b/test/CodeGen/SystemZ/frame-14.ll @@ -1,9 +1,13 @@ ; Test the handling of base + displacement addresses for large frames, ; in cases where both 12-bit and 20-bit displacements are allowed. +; The tests here assume z10 register pressure, without the high words +; being available. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \ +; RUN: FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \ +; RUN: FileCheck -check-prefix=CHECK-FP %s ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s - ; This file tests what happens when a displacement is converted from ; being relative to the start of a frame object to being relative to ; the frame itself. In some cases the test is only possible if two diff --git a/test/CodeGen/SystemZ/frame-15.ll b/test/CodeGen/SystemZ/frame-15.ll index d8b291d0178..b3c95e73c1a 100644 --- a/test/CodeGen/SystemZ/frame-15.ll +++ b/test/CodeGen/SystemZ/frame-15.ll @@ -1,8 +1,11 @@ ; Test the handling of base + index + 12-bit displacement addresses for -; large frames, in cases where no 20-bit form exists. +; large frames, in cases where no 20-bit form exists. The tests here +; assume z10 register pressure, without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \ +; RUN: FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \ +; RUN: FileCheck -check-prefix=CHECK-FP %s declare void @foo(float *%ptr1, float *%ptr2) diff --git a/test/CodeGen/SystemZ/frame-16.ll b/test/CodeGen/SystemZ/frame-16.ll index 9f43b4947f0..f7e2dfa3514 100644 --- a/test/CodeGen/SystemZ/frame-16.ll +++ b/test/CodeGen/SystemZ/frame-16.ll @@ -1,8 +1,12 @@ ; Test the handling of base + index + displacement addresses for large frames, ; in cases where both 12-bit and 20-bit displacements are allowed. +; The tests here assume z10 register pressure, without the high words +; being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \ +; RUN: FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \ +; RUN: FileCheck -check-prefix=CHECK-FP %s ; This file tests what happens when a displacement is converted from ; being relative to the start of a frame object to being relative to diff --git a/test/CodeGen/SystemZ/frame-18.ll b/test/CodeGen/SystemZ/frame-18.ll index 57d6f7d4db2..21dfc1238a1 100644 --- a/test/CodeGen/SystemZ/frame-18.ll +++ b/test/CodeGen/SystemZ/frame-18.ll @@ -1,6 +1,7 @@ -; Test spilling of GPRs. +; Test spilling of GPRs. The tests here assume z10 register pressure, +; without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; We need to allocate a 4-byte spill slot, rounded to 8 bytes. The frame ; size should be exactly 160 + 8 = 168. diff --git a/test/CodeGen/SystemZ/int-add-11.ll b/test/CodeGen/SystemZ/int-add-11.ll index 212334e83c0..679c206094f 100644 --- a/test/CodeGen/SystemZ/int-add-11.ll +++ b/test/CodeGen/SystemZ/int-add-11.ll @@ -1,6 +1,7 @@ -; Test 32-bit additions of constants to memory. +; Test 32-bit additions of constants to memory. The tests here +; assume z10 register pressure, without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check additions of 1. define void @f1(i32 *%ptr) { diff --git a/test/CodeGen/SystemZ/int-conv-02.ll b/test/CodeGen/SystemZ/int-conv-02.ll index 18cfd4a87fa..dd7760d08cf 100644 --- a/test/CodeGen/SystemZ/int-conv-02.ll +++ b/test/CodeGen/SystemZ/int-conv-02.ll @@ -1,6 +1,7 @@ -; Test zero extensions from a byte to an i32. +; Test zero extensions from a byte to an i32. The tests here +; assume z10 register pressure, without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Test register extension, starting with an i32. define i32 @f1(i32 %a) { diff --git a/test/CodeGen/SystemZ/int-conv-06.ll b/test/CodeGen/SystemZ/int-conv-06.ll index 9c95badb2c0..33860d12270 100644 --- a/test/CodeGen/SystemZ/int-conv-06.ll +++ b/test/CodeGen/SystemZ/int-conv-06.ll @@ -1,6 +1,7 @@ -; Test zero extensions from a halfword to an i32. +; Test zero extensions from a halfword to an i32. The tests here +; assume z10 register pressure, without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Test register extension, starting with an i32. define i32 @f1(i32 %a) { diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll index 85de6dc6af2..8a5d4874f68 100644 --- a/test/CodeGen/SystemZ/risbg-01.ll +++ b/test/CodeGen/SystemZ/risbg-01.ll @@ -1,6 +1,7 @@ ; Test sequences that can use RISBG with a zeroed first operand. +; The tests here assume that RISBLG isn't available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Test an extraction of bit 0 from a right-shifted value. define i32 @f1(i32 %foo) { diff --git a/test/CodeGen/SystemZ/setcc-01.ll b/test/CodeGen/SystemZ/setcc-01.ll index 5313215f118..4626760fa25 100644 --- a/test/CodeGen/SystemZ/setcc-01.ll +++ b/test/CodeGen/SystemZ/setcc-01.ll @@ -1,6 +1,7 @@ -; Test SETCC for every integer condition. +; Test SETCC for every integer condition. The tests here assume that +; RISBLG isn't available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Test CC in { 0 }, with 3 don't care. define i32 @f1(i32 %a, i32 %b) { diff --git a/test/CodeGen/SystemZ/setcc-02.ll b/test/CodeGen/SystemZ/setcc-02.ll index 178822277d1..6a7be47a92b 100644 --- a/test/CodeGen/SystemZ/setcc-02.ll +++ b/test/CodeGen/SystemZ/setcc-02.ll @@ -1,6 +1,7 @@ -; Test SETCC for every floating-point condition. +; Test SETCC for every floating-point condition. The tests here assume that +; RISBLG isn't available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Test CC in { 0 } define i32 @f1(float %a, float %b) { diff --git a/test/CodeGen/SystemZ/spill-01.ll b/test/CodeGen/SystemZ/spill-01.ll index 9de89d69b99..ca64a88f2a0 100644 --- a/test/CodeGen/SystemZ/spill-01.ll +++ b/test/CodeGen/SystemZ/spill-01.ll @@ -1,6 +1,7 @@ -; Test spilling using MVC. +; Test spilling using MVC. The tests here assume z10 register pressure, +; without the high words being available. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s declare void @foo()