mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
45c8d2bc9c
commit
793e79601f
@ -994,7 +994,8 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
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i != NumOps; ++i)
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RegList.push_back(MI->getOperand(i).getReg());
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break;
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case ARM::STR_PRE:
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case ARM::STR_PRE_IMM:
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case ARM::STR_PRE_REG:
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assert(MI->getOperand(2).getReg() == ARM::SP &&
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"Only stack pointer as a source reg is supported");
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RegList.push_back(SrcReg);
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@ -93,7 +93,8 @@ static bool isCSRestore(MachineInstr *MI,
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return false;
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return true;
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}
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if ((MI->getOpcode() == ARM::LDR_POST ||
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if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
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MI->getOpcode() == ARM::LDR_POST_REG ||
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MI->getOpcode() == ARM::t2LDR_POST) &&
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isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
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MI->getOperand(1).getReg() == ARM::SP)
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@ -590,7 +591,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
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.addReg(ARM::SP).setMIFlags(MIFlags);
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// ARM mode needs an extra reg0 here due to addrmode2. Will go away once
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// that refactoring is complete (eventually).
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if (StrOpc == ARM::STR_PRE) {
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if (StrOpc == ARM::STR_PRE_REG || StrOpc == ARM::STR_PRE_IMM) {
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MIB.addReg(0);
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MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift));
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} else
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@ -665,7 +666,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
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.addReg(ARM::SP);
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// ARM mode needs an extra reg0 here due to addrmode2. Will go away once
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// that refactoring is complete (eventually).
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if (LdrOpc == ARM::LDR_POST) {
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if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
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MIB.addReg(0);
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MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
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} else
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@ -687,7 +688,7 @@ bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
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unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;
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unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM;
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unsigned FltOpc = ARM::VSTMDDB_UPD;
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emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register,
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MachineInstr::FrameSetup);
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@ -711,7 +712,7 @@ bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
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unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
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unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST;
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unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
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unsigned FltOpc = ARM::VLDMDIA_UPD;
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emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);
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emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
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@ -129,7 +129,9 @@ public:
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return true;
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}
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bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
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bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
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SDValue &Offset, SDValue &Opc);
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bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
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SDValue &Offset, SDValue &Opc);
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bool SelectAddrMode3(SDValue N, SDValue &Base,
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SDValue &Offset, SDValue &Opc);
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@ -714,7 +716,7 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
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return AM2_SHOP;
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}
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bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
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bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
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SDValue &Offset, SDValue &Opc) {
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unsigned Opcode = Op->getOpcode();
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ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
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@ -723,13 +725,8 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
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ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
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? ARM_AM::add : ARM_AM::sub;
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int Val;
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if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
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ARM_AM::no_shift),
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MVT::i32);
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return true;
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}
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if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
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return false;
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Offset = N;
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
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@ -755,6 +752,28 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
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return true;
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}
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bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
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SDValue &Offset, SDValue &Opc) {
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unsigned Opcode = Op->getOpcode();
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ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
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? cast<LoadSDNode>(Op)->getAddressingMode()
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: cast<StoreSDNode>(Op)->getAddressingMode();
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ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
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? ARM_AM::add : ARM_AM::sub;
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int Val;
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if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
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ARM_AM::no_shift),
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MVT::i32);
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return true;
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}
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return false;
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}
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bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
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SDValue &Base, SDValue &Offset,
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@ -1298,9 +1317,14 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
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unsigned Opcode = 0;
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bool Match = false;
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if (LoadedVT == MVT::i32 &&
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SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
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Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
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SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
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Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST_IMM;
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Match = true;
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} else if (LoadedVT == MVT::i32 &&
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SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
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Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST_REG;
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Match = true;
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} else if (LoadedVT == MVT::i16 &&
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SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
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Match = true;
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@ -1314,9 +1338,12 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
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Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
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}
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} else {
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if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
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if (SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
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Match = true;
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Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
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Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST_IMM;
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} else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
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Match = true;
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Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST_REG;
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}
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}
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}
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@ -507,22 +507,41 @@ class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
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let Inst{20} = isLd; // L bit
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let Inst{15-12} = Rt;
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}
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class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
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class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
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IndexMode im, Format f, InstrItinClass itin, string opc,
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string asm, string cstr, list<dag> pattern>
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: AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
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pattern> {
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// AM2 store w/ two operands: (GPR, am2offset)
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{25} = 1;
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-5} = offset{11-5};
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let Inst{4} = 0;
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let Inst{3-0} = offset{3-0};
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}
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class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
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IndexMode im, Format f, InstrItinClass itin, string opc,
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string asm, string cstr, list<dag> pattern>
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: AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
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pattern> {
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// AM2 store w/ two operands: (GPR, am2offset)
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = 0;
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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}
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// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
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// but for now use this class for STRT and STRBT.
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class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
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@ -31,13 +31,15 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
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switch (Opc) {
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default: break;
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case ARM::LDR_PRE:
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case ARM::LDR_POST:
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case ARM::LDR_POST_IMM:
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case ARM::LDR_POST_REG:
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return ARM::LDRi12;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE:
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case ARM::LDRB_POST:
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case ARM::LDRB_POST_IMM:
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case ARM::LDRB_POST_REG:
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return ARM::LDRBi12;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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@ -45,14 +47,18 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE:
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case ARM::STR_POST:
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case ARM::STR_PRE_IMM:
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case ARM::STR_PRE_REG:
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case ARM::STR_POST_IMM:
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case ARM::STR_POST_REG:
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return ARM::STRi12;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE:
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case ARM::STRB_POST:
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case ARM::STRB_PRE_IMM:
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case ARM::STRB_PRE_REG:
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case ARM::STRB_POST_IMM:
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case ARM::STRB_POST_REG:
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return ARM::STRBi12;
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}
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@ -503,6 +503,7 @@ def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
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return Imm >= 0 && Imm < 32;
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}]> {
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let EncoderMethod = "getImmMinusOneOpValue";
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let DecoderMethod = "DecodeImmMinusOneOperand";
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}
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// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
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@ -606,14 +607,23 @@ def addrmode2 : Operand<i32>,
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def am2offset : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2Offset",
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def am2offset_reg : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
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[], [SDNPWantRoot]> {
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let EncoderMethod = "getAddrMode2OffsetOpValue";
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let PrintMethod = "printAddrMode2OffsetOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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def am2offset_imm : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
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[], [SDNPWantRoot]> {
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let EncoderMethod = "getAddrMode2OffsetOpValue";
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let PrintMethod = "printAddrMode2OffsetOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmode3 := reg +/- reg
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// addrmode3 := reg +/- imm8
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//
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@ -1845,7 +1855,7 @@ multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
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(ins addrmode2:$addr), IndexModePre, LdFrm, itin,
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opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
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// {17-14} Rn
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// {13} 1 == Rm, 0 == imm12
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// {13} reg vs. imm
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<18> addr;
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@ -1855,19 +1865,35 @@ multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
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}
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def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset:$offset),
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def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset_reg:$offset),
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IndexModePost, LdFrm, itin,
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = 1;
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset_imm:$offset),
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IndexModePost, LdFrm, itin,
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{25} = 0;
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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}
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@ -1998,36 +2024,69 @@ def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
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"strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
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// Indexed stores
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def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
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def STR_PRE_REG : AI2stridx_reg<0, 1, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
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IndexModePre, StFrm, IIC_iStore_ru,
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"str", "\t$Rt, [$Rn, $offset]!",
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"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
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[(set GPR:$Rn_wb,
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(pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
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(pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
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def STR_PRE_IMM : AI2stridx_imm<0, 1, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
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IndexModePre, StFrm, IIC_iStore_ru,
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"str", "\t$Rt, [$Rn, $offset]!",
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"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
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[(set GPR:$Rn_wb,
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(pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
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def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
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def STR_POST_REG : AI2stridx_reg<0, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
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IndexModePost, StFrm, IIC_iStore_ru,
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"str", "\t$Rt, [$Rn], $offset",
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"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
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[(set GPR:$Rn_wb,
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(post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
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(post_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
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def STR_POST_IMM : AI2stridx_imm<0, 0, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
|
||||
IndexModePost, StFrm, IIC_iStore_ru,
|
||||
"str", "\t$Rt, [$Rn], $offset",
|
||||
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
|
||||
[(set GPR:$Rn_wb,
|
||||
(post_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
|
||||
|
||||
def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
|
||||
|
||||
def STRB_PRE_REG : AI2stridx_reg<1, 1, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
|
||||
IndexModePre, StFrm, IIC_iStore_bh_ru,
|
||||
"strb", "\t$Rt, [$Rn, $offset]!",
|
||||
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
|
||||
[(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
|
||||
GPR:$Rn, am2offset:$offset))]>;
|
||||
def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
|
||||
GPR:$Rn, am2offset_reg:$offset))]>;
|
||||
def STRB_PRE_IMM : AI2stridx_imm<1, 1, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
|
||||
IndexModePre, StFrm, IIC_iStore_bh_ru,
|
||||
"strb", "\t$Rt, [$Rn, $offset]!",
|
||||
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
|
||||
[(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
|
||||
GPR:$Rn, am2offset_imm:$offset))]>;
|
||||
|
||||
def STRB_POST_REG: AI2stridx_reg<1, 0, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
|
||||
IndexModePost, StFrm, IIC_iStore_bh_ru,
|
||||
"strb", "\t$Rt, [$Rn], $offset",
|
||||
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
|
||||
[(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
|
||||
GPR:$Rn, am2offset:$offset))]>;
|
||||
GPR:$Rn, am2offset_reg:$offset))]>;
|
||||
def STRB_POST_IMM: AI2stridx_imm<1, 0, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
|
||||
IndexModePost, StFrm, IIC_iStore_bh_ru,
|
||||
"strb", "\t$Rt, [$Rn], $offset",
|
||||
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
|
||||
[(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
|
||||
GPR:$Rn, am2offset_imm:$offset))]>;
|
||||
|
||||
|
||||
def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
|
||||
|
||||
@ -766,7 +766,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc,
|
||||
case ARM::LDRi12:
|
||||
return ARM::LDR_PRE;
|
||||
case ARM::STRi12:
|
||||
return ARM::STR_PRE;
|
||||
return ARM::STR_PRE_IMM;
|
||||
case ARM::VLDRS:
|
||||
return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
|
||||
case ARM::VLDRD:
|
||||
@ -790,9 +790,9 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
|
||||
ARM_AM::AddrOpc Mode) {
|
||||
switch (Opc) {
|
||||
case ARM::LDRi12:
|
||||
return ARM::LDR_POST;
|
||||
return ARM::LDR_POST_IMM;
|
||||
case ARM::STRi12:
|
||||
return ARM::STR_POST;
|
||||
return ARM::STR_POST_IMM;
|
||||
case ARM::VLDRS:
|
||||
return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
|
||||
case ARM::VLDRD:
|
||||
|
||||
@ -639,7 +639,8 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
|
||||
MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
|
||||
MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
|
||||
MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
|
||||
MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
|
||||
MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I
|
||||
MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I
|
||||
MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
|
||||
MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
|
||||
MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
|
||||
|
||||
Loading…
Reference in New Issue
Block a user