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Fix coordination for using R4 in Thumb1 as a scratch for SP restore.
The logic for reserving R4 for use as a scratch needs to match that for actually using it. Also, it's not necessary for immediate <=508, so adjust the value checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132934 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -841,9 +841,14 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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if (AFI->getVarArgsRegSaveSize() > 0)
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if (AFI->getVarArgsRegSaveSize() > 0)
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MF.getRegInfo().setPhysRegUsed(ARM::LR);
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MF.getRegInfo().setPhysRegUsed(ARM::LR);
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// Spill R4 if Thumb1 epilogue has to restore SP from FP since
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// Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
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// for sure what the stack size will be, but for this, an estimate is good
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// enough. If there anything changes it, it'll be a spill, which implies
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// we've used all the registers and so R4 is already used, so not marking
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// it here will be OK.
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// FIXME: It will be better just to find spare register here.
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// FIXME: It will be better just to find spare register here.
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if (MFI->hasVarSizedObjects())
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unsigned StackSize = estimateStackSize(MF);
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if (MFI->hasVarSizedObjects() || StackSize > 508)
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MF.getRegInfo().setPhysRegUsed(ARM::R4);
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MF.getRegInfo().setPhysRegUsed(ARM::R4);
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}
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}
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@ -136,8 +136,8 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
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.addFrameIndex(FramePtrSpillFI).addImm(0)
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.addFrameIndex(FramePtrSpillFI).addImm(0)
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.setMIFlags(MachineInstr::FrameSetup);
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.setMIFlags(MachineInstr::FrameSetup);
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if (NumBytes > 7)
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if (NumBytes > 508)
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// If offset is > 7 then sp cannot be adjusted in a single instruction,
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// If offset is > 508 then sp cannot be adjusted in a single instruction,
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// try restoring from fp instead.
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// try restoring from fp instead.
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AFI->setShouldRestoreSPFromFP(true);
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AFI->setShouldRestoreSPFromFP(true);
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}
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}
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