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https://github.com/c64scene-ar/llvm-6502.git
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Add AVX SSE3 replicate and convert instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3161,10 +3161,18 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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//===---------------------------------------------------------------------===//
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// SSE3 Instructions
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// SSE3 - Conversion Instructions
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//===---------------------------------------------------------------------===//
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// Conversion Instructions
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
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def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
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def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
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def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
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}
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def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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@ -3174,33 +3182,44 @@ def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
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// Move Instructions
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def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movshdup\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (movshdup
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VR128:$src, (undef))))]>;
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def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movshdup\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (movshdup
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(memopv4f32 addr:$src), (undef)))]>;
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//===---------------------------------------------------------------------===//
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// SSE3 - Move Instructions
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//===---------------------------------------------------------------------===//
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def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movsldup\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (movsldup
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// Replicate Single FP
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multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
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def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (v4f32 (rep_frag
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VR128:$src, (undef))))]>;
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def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"movsldup\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (movsldup
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def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (rep_frag
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(memopv4f32 addr:$src), (undef)))]>;
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}
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def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movddup\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
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def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"movddup\t{$src, $dst|$dst, $src}",
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
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defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
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defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
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}
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defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
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defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
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// Replicate Double FP
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multiclass sse3_replicate_dfp<string OpcodeStr> {
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def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
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def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
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(undef))))]>;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
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defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
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defm MOVDDUP : sse3_replicate_dfp<"movddup">;
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def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
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(undef)),
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@ -3217,6 +3236,10 @@ def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
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(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
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}
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//===---------------------------------------------------------------------===//
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// SSE3 Instructions
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//===---------------------------------------------------------------------===//
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// Arithmetic
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let Constraints = "$src1 = $dst" in {
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def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
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@ -11530,3 +11530,39 @@
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// CHECK: encoding: [0xc5,0xfa,0x7e,0x08]
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vmovq (%eax), %xmm1
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// CHECK: vcvtpd2dq %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xfb,0xe6,0xd1]
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vcvtpd2dq %xmm1, %xmm2
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// CHECK: vcvtdq2pd %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xfa,0xe6,0xd1]
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vcvtdq2pd %xmm1, %xmm2
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// CHECK: vcvtdq2pd (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xfa,0xe6,0x10]
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vcvtdq2pd (%eax), %xmm2
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// CHECK: vmovshdup %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xfa,0x16,0xd1]
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vmovshdup %xmm1, %xmm2
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// CHECK: vmovshdup (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xfa,0x16,0x10]
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vmovshdup (%eax), %xmm2
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// CHECK: vmovsldup %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xfa,0x12,0xd1]
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vmovsldup %xmm1, %xmm2
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// CHECK: vmovsldup (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xfa,0x12,0x10]
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vmovsldup (%eax), %xmm2
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// CHECK: vmovddup %xmm1, %xmm2
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// CHECK: encoding: [0xc5,0xfb,0x12,0xd1]
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vmovddup %xmm1, %xmm2
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// CHECK: vmovddup (%eax), %xmm2
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// CHECK: encoding: [0xc5,0xfb,0x12,0x10]
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vmovddup (%eax), %xmm2
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@ -1578,3 +1578,39 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc4,0x61,0xf9,0x7e,0xf0]
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vmovq %xmm14, %rax
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// CHECK: vcvtpd2dq %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xe3]
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vcvtpd2dq %xmm11, %xmm12
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// CHECK: vcvtdq2pd %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x7a,0xe6,0xe3]
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vcvtdq2pd %xmm11, %xmm12
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// CHECK: vcvtdq2pd (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x7a,0xe6,0x20]
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vcvtdq2pd (%rax), %xmm12
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// CHECK: vmovshdup %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x7a,0x16,0xe3]
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vmovshdup %xmm11, %xmm12
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// CHECK: vmovshdup (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x7a,0x16,0x20]
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vmovshdup (%rax), %xmm12
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// CHECK: vmovsldup %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x7a,0x12,0xe3]
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vmovsldup %xmm11, %xmm12
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// CHECK: vmovsldup (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x7a,0x12,0x20]
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vmovsldup (%rax), %xmm12
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// CHECK: vmovddup %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x7b,0x12,0xe3]
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vmovddup %xmm11, %xmm12
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// CHECK: vmovddup (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x7b,0x12,0x20]
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vmovddup (%rax), %xmm12
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