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Be more lenient on tied operand matching for MUL.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-08-19 22:30:46 +00:00
parent 0c9acfcb50
commit 7a01069420
2 changed files with 12 additions and 5 deletions
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15
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -2382,16 +2382,23 @@ cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
// The second source operand must be the same register as the destination
// operand.
if (Operands.size() == 6 &&
((ARMOperand*)Operands[3])->getReg() !=
((ARMOperand*)Operands[5])->getReg()) {
(((ARMOperand*)Operands[3])->getReg() !=
((ARMOperand*)Operands[5])->getReg()) &&
(((ARMOperand*)Operands[3])->getReg() !=
((ARMOperand*)Operands[4])->getReg())) {
Error(Operands[3]->getStartLoc(),
"destination register must match second source register");
"destination register must match source register");
return false;
}
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
Inst.addOperand(Inst.getOperand(0));
// If we have a three-operand form, use that, else the second source operand
// is just the destination operand again.
if (Operands.size() == 6)
((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
else
Inst.addOperand(Inst.getOperand(0));
((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
return true;