From 7a025c8b4dedee6856d9f118386ef0296eddece0 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 16 Oct 2005 20:02:19 +0000 Subject: [PATCH] Add a bunch of info about the isel autogenerator. Review appreciated! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23763 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/CodeGenerator.html | 201 +++++++++++++++++++++++++++++++++------- 1 file changed, 168 insertions(+), 33 deletions(-) diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index 1b699dd9822..bc99fb24928 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -731,8 +731,10 @@ instruction selector to be generated from these .td files.

The SelectionDAG provides an abstraction for code representation in a way that is amenable to instruction selection using automatic techniques (e.g. dynamic-programming based optimal pattern matching selectors), It is also -well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a -large variety of very-low-level (but target-independent) +well suited to other phases of code generation; in particular, +instruction scheduling (SelectionDAG's are very close to scheduling DAGs +post-selection). Additionally, the SelectionDAG provides a host representation +where a large variety of very-low-level (but target-independent) optimizations may be performed: ones which require extensive information about the instructions efficiently supported by the target. @@ -741,11 +743,10 @@ efficiently supported by the target.

The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the SDNode class. The primary payload of the SDNode is its -operation code (Opcode) that indicates what operation the node performs. +operation code (Opcode) that indicates what operation the node performs and +the operands to the operation. The various operation node types are described at the top of the -include/llvm/CodeGen/SelectionDAGNodes.h file. Depending on the -operation, nodes may contain additional information (e.g. the condition code -for a SETCC node) contained in a derived class.

+include/llvm/CodeGen/SelectionDAGNodes.h file.

Although most operations define a single value, each node in the graph may define multiple values. For example, a combined div/rem operation will define @@ -779,8 +780,10 @@ block function, this would be the return node.

One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal" DAG. A legal DAG for a target is one that only uses supported operations and -supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16, -or i64 type would be illegal. The legalize +supported types. On a 32-bit PowerPC, for example, a DAG with any values of i1, +i8, i16, +or i64 type would be illegal, as would a DAG that uses a SREM or UREM operation. +The legalize phase is responsible for turning an illegal DAG into a legal DAG.

@@ -841,7 +844,8 @@ intent of this pass is to expose as much low-level, target-specific details to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM add turns into an SDNode add while a geteelementptr is expanded into the obvious arithmetic). This pass requires target-specific hooks to lower calls and -returns, varargs, etc. For these features, the TargetLowering interface is +returns, varargs, etc. For these features, the TargetLowering interface is used.

@@ -860,34 +864,41 @@ tasks:

  1. Convert values of unsupported types to values of supported types.

    -

    There are two main ways of doing this: promoting a small type to a larger - type (e.g. f32 -> f64, or i16 -> i32), and breaking up large - integer types - to smaller ones (e.g. implementing i64 with i32 operations where - possible). Type conversions can insert sign and zero extensions as +

    There are two main ways of doing this: converting small types to + larger types ("promoting"), and breaking up large integer types + into smaller ones ("expanding"). For example, a target might require + that all f32 values are promoted to f64 and that all i1/i8/i16 values + are promoted to i32. The same target might require that all i64 values + be expanded into i32 values. These changes can insert sign and zero + extensions as needed to make sure that the final code has the same behavior as the input.

    +

    A target implementation tells the legalizer which types are supported + (and which register class to use for them) by calling the + "addRegisterClass" method in its TargetLowering constructor.

    2. -

  2. Eliminate operations that are not supported by the target in a supported - type.

    -

    Targets often have wierd constraints, such as not supporting every +

  3. Eliminate operations that are not supported by the target.

    +

    Targets often have weird constraints, such as not supporting every operation on every supported datatype (e.g. X86 does not support byte - conditional moves). Legalize takes care of either open-coding another - sequence of operations to emulate the operation (this is known as - expansion), promoting to a larger type that supports the operation + conditional moves and PowerPC does not support sign-extending loads from + a 16-bit memory location). Legalize takes care by open-coding + another sequence of operations to emulate the operation ("expansion"), by + promoting to a larger type that supports the operation (promotion), or using a target-specific hook to implement the - legalization.

    + legalization (custom).

    +

    A target implementation tells the legalizer which operations are not + supported (and which of the above three actions to take) by calling the + "setOperationAction" method in its TargetLowering constructor.

-Instead of using a Legalize pass, we could require that every target-specific -selector supports and expands every -operator and type even if they are not supported and may require many -instructions to implement (in fact, this is the approach taken by the -"simple" selectors). However, using a Legalize pass allows all of the -cannonicalization patterns to be shared across targets which makes it very +Prior to the existance of the Legalize pass, we required that every +target selector supported and handled every +operator and type even if they are not natively supported. The introduction of +the Legalize phase allows all of the +cannonicalization patterns to be shared across targets, and makes it very easy to optimize the cannonicalized code because it is still in the form of a DAG.

@@ -908,8 +919,8 @@ immediately after the DAG is built and once after legalization. The first run of the pass allows the initial code to be cleaned up (e.g. performing optimizations that depend on knowing that the operators have restricted type inputs). The second run of the pass cleans up the messy code generated by the -Legalize pass, allowing Legalize to be very simple since it can ignore many -special cases. +Legalize pass, which allows Legalize to be very simple (it can focus on making +code legal instead of focusing on generating good and legal code).

@@ -944,10 +955,134 @@ International Conference on Compiler Construction (CC) 2004

The Select phase is the bulk of the target-specific code for instruction -selection. This phase takes a legal SelectionDAG as input, and does simple -pattern matching on the DAG to generate code. In time, the Select phase will -be automatically generated from the target's InstrInfo.td file, which is why we -want to make the Select phase as simple and mechanical as possible.

+selection. This phase takes a legal SelectionDAG as input, +pattern matches the instructions supported by the target to this DAG, and +produces a new DAG of target code. For example, consider the following LLVM +fragment:

+ +
+   %t1 = add float %W, %X
+   %t2 = mul float %t1, %Y
+   %t3 = add float %t2, %Z
+
+ +

This LLVM code corresponds to a SelectionDAG that looks basically like this: +

+ +
+  (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
+
+ +

If a target supports floating pointer multiple-and-add (FMA) operations, one +of the adds can be merged with the multiply. On the PowerPC, for example, the +output of the instruction selector might look like this DAG:

+ +
+  (FMADDS (FADDS W, X), Y, Z)
+
+ +

+The FMADDS instruction is a ternary instruction that multiplies its first two +operands and adds the third (as single-precision floating-point numbers). The +FADDS instruction is a simple binary single-precision add instruction. To +perform this pattern match, the PowerPC backend includes the following +instruction definitions: +

+ +
+def FMADDS : AForm_1<59, 29,
+                    (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+                    "fmadds $FRT, $FRA, $FRC, $FRB",
+                    [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
+                                           F4RC:$FRB))]>;
+def FADDS : AForm_2<59, 21,
+                    (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
+                    "fadds $FRT, $FRA, $FRB",
+                    [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
+
+ +

The portion of the instruction definition in bold indicates the pattern used +to match the instruction. The DAG operators (like fmul/fadd) +are defined in the lib/Target/TargetSelectionDAG.td file. +"F4RC" is the register class of the input and result values.

+ +

The TableGen DAG instruction selector generator reads the instruction +patterns in the .td and automatically builds parts of the pattern matching code +for your target. It has the following strengths:

+ + + +

+While it has many strengths, the system currently has some limitations, +primarily because it is a work in progress and is not yet finished: +

+ +