The code generator backend maps instruction operands to fields in +the instruction. Operands are assigned to unbound fields in the instruction in +the order they are defined. Fields are bound when they are assigned a value. +For example, the Sparc target defines the XNORrr instruction as a F3_1 format +instruction having three operands.
++def XNORrr : F3_1<2, 0b000111, + (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), + "xnor $b, $c, $dst", + [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; +
The instruction templates in SparcInstrFormats.td show the base class for F3_1 is InstSP.
+
+class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
+ field bits<32> Inst;
+ let Namespace = "SP";
+ bits<2> op;
+ let Inst{31-30} = op;
+ dag OutOperandList = outs;
+ dag InOperandList = ins;
+ let AsmString = asmstr;
+ let Pattern = pattern;
+}
++InstSP leaves the op field unbound. +
+
+class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSP<outs, ins, asmstr, pattern> {
+ bits<5> rd;
+ bits<6> op3;
+ bits<5> rs1;
+ let op{1} = 1; // Op = 2 or 3
+ let Inst{29-25} = rd;
+ let Inst{24-19} = op3;
+ let Inst{18-14} = rs1;
+}
++F3 binds the op field and defines the rd, op3, and rs1 fields. F3 format instructions will +bind the operands rd, op3, and rs1 fields. +
+
+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+ string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
+ bits<8> asi = 0; // asi not currently used
+ bits<5> rs2;
+ let op = opVal;
+ let op3 = op3val;
+ let Inst{13} = 0; // i field = 0
+ let Inst{12-5} = asi; // address space identifier
+ let Inst{4-0} = rs2;
+}
++F3_1 binds the op3 field and defines the rs2 fields. F3_1 format instructions will +bind the operands to the rd, rs1, and rs2 fields. This results in the XNORrr instruction +binding $dst, $b, and $c operands to the rd, rs1, and rs2 fields respectively. +
+