mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-21 18:24:23 +00:00
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
@ -141,6 +141,22 @@ static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
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@ -2560,3 +2576,447 @@ static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
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return true;
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}
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static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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switch (size) {
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default:
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return false;
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case 0:
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if (fieldFromInstruction32(Insn, 4, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 5, 3);
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break;
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case 1:
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if (fieldFromInstruction32(Insn, 5, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 6, 2);
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 2;
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break;
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case 2:
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if (fieldFromInstruction32(Insn, 6, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 7, 1);
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if (fieldFromInstruction32(Insn, 4, 2) != 0)
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align = 4;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (Rm != 0xF) { // Writeback
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
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return false;
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}
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(align));
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if (Rm != 0xF && Rm != 0xD) {
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if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
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return false;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(index));
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return true;
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}
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static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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switch (size) {
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default:
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return false;
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case 0:
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if (fieldFromInstruction32(Insn, 4, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 5, 3);
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break;
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case 1:
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if (fieldFromInstruction32(Insn, 5, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 6, 2);
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 2;
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break;
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case 2:
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if (fieldFromInstruction32(Insn, 6, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 7, 1);
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if (fieldFromInstruction32(Insn, 4, 2) != 0)
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align = 4;
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}
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if (Rm != 0xF) { // Writeback
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
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return false;
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}
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(align));
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if (Rm != 0xF && Rm != 0xD) {
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if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
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return false;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(index));
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return true;
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}
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static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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unsigned inc = 1;
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switch (size) {
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default:
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return false;
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case 0:
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index = fieldFromInstruction32(Insn, 5, 3);
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 2;
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break;
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case 1:
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index = fieldFromInstruction32(Insn, 6, 2);
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 4;
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if (fieldFromInstruction32(Insn, 5, 1))
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inc = 2;
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break;
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case 2:
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if (fieldFromInstruction32(Insn, 5, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 7, 1);
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if (fieldFromInstruction32(Insn, 4, 1) != 0)
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align = 8;
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if (fieldFromInstruction32(Insn, 6, 1))
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inc = 2;
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break;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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if (Rm != 0xF) { // Writeback
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
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return false;
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}
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(align));
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if (Rm != 0xF && Rm != 0xD) {
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if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
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return false;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(index));
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return true;
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}
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static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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unsigned inc = 1;
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switch (size) {
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default:
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return false;
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case 0:
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index = fieldFromInstruction32(Insn, 5, 3);
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 2;
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break;
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case 1:
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index = fieldFromInstruction32(Insn, 6, 2);
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 4;
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if (fieldFromInstruction32(Insn, 5, 1))
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inc = 2;
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break;
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case 2:
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if (fieldFromInstruction32(Insn, 5, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 7, 1);
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if (fieldFromInstruction32(Insn, 4, 1) != 0)
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align = 8;
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if (fieldFromInstruction32(Insn, 6, 1))
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inc = 2;
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break;
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}
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if (Rm != 0xF) { // Writeback
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
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return false;
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}
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(align));
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if (Rm != 0xF && Rm != 0xD) {
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if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
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return false;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(index));
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return true;
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}
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static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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unsigned inc = 1;
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switch (size) {
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default:
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return false;
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case 0:
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if (fieldFromInstruction32(Insn, 4, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 5, 3);
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break;
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case 1:
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if (fieldFromInstruction32(Insn, 4, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 6, 2);
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if (fieldFromInstruction32(Insn, 5, 1))
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inc = 2;
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break;
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case 2:
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if (fieldFromInstruction32(Insn, 4, 2))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 7, 1);
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if (fieldFromInstruction32(Insn, 6, 1))
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inc = 2;
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break;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
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if (Rm != 0xF) { // Writeback
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
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return false;
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}
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(align));
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if (Rm != 0xF && Rm != 0xD) {
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if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
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return false;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(index));
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return true;
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}
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static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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unsigned inc = 1;
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switch (size) {
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default:
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return false;
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case 0:
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if (fieldFromInstruction32(Insn, 4, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 5, 3);
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break;
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case 1:
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if (fieldFromInstruction32(Insn, 4, 1))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 6, 2);
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if (fieldFromInstruction32(Insn, 5, 1))
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inc = 2;
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break;
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case 2:
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if (fieldFromInstruction32(Insn, 4, 2))
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return false; // UNDEFINED
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index = fieldFromInstruction32(Insn, 7, 1);
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if (fieldFromInstruction32(Insn, 6, 1))
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inc = 2;
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break;
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}
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if (Rm != 0xF) { // Writeback
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
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return false;
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}
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(align));
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if (Rm != 0xF && Rm != 0xD) {
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if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
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return false;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(index));
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return true;
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}
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static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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unsigned inc = 1;
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switch (size) {
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default:
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return false;
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case 0:
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 4;
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index = fieldFromInstruction32(Insn, 5, 3);
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break;
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case 1:
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 8;
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index = fieldFromInstruction32(Insn, 6, 2);
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if (fieldFromInstruction32(Insn, 5, 1))
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inc = 2;
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break;
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case 2:
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if (fieldFromInstruction32(Insn, 4, 2))
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align = 4 << fieldFromInstruction32(Insn, 4, 2);
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index = fieldFromInstruction32(Insn, 7, 1);
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if (fieldFromInstruction32(Insn, 6, 1))
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inc = 2;
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break;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
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if (Rm != 0xF) { // Writeback
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
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return false;
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}
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if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(align));
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if (Rm != 0xF && Rm != 0xD) {
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if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
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return false;
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}
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if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
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if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
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Inst.addOperand(MCOperand::CreateImm(index));
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return true;
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}
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static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
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unsigned size = fieldFromInstruction32(Insn, 10, 2);
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unsigned align = 0;
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unsigned index = 0;
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unsigned inc = 1;
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switch (size) {
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default:
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return false;
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case 0:
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if (fieldFromInstruction32(Insn, 4, 1))
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align = 4;
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index = fieldFromInstruction32(Insn, 5, 3);
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break;
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case 1:
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if (fieldFromInstruction32(Insn, 4, 1))
|
||||
align = 8;
|
||||
index = fieldFromInstruction32(Insn, 6, 2);
|
||||
if (fieldFromInstruction32(Insn, 5, 1))
|
||||
inc = 2;
|
||||
break;
|
||||
case 2:
|
||||
if (fieldFromInstruction32(Insn, 4, 2))
|
||||
align = 4 << fieldFromInstruction32(Insn, 4, 2);
|
||||
index = fieldFromInstruction32(Insn, 7, 1);
|
||||
if (fieldFromInstruction32(Insn, 6, 1))
|
||||
inc = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
if (Rm != 0xF) { // Writeback
|
||||
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
|
||||
return false;
|
||||
}
|
||||
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
|
||||
Inst.addOperand(MCOperand::CreateImm(align));
|
||||
if (Rm != 0xF && Rm != 0xD) {
|
||||
if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
|
||||
if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
|
||||
if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
|
||||
if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
|
||||
Inst.addOperand(MCOperand::CreateImm(index));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user