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Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -48,6 +48,8 @@ def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
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"Enable divide instructions">;
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def FeatureT2ExtractPack: SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
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"Enable Thumb2 extract and pack instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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// Some processors have multiply-accumulate instructions that don't
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// play nicely with other VFP instructions, and it's generally better
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@ -129,7 +131,7 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries,
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// V7 Processors.
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def : Processor<"cortex-a8", CortexA8Itineraries,
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
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FeatureNEONForFP, FeatureT2ExtractPack]>;
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FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2ExtractPack]>;
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def : Processor<"cortex-a9", CortexA9Itineraries,
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack]>;
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def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
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@ -54,6 +54,9 @@ protected:
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/// the VML[AS] instructions are slow (if so, don't use them).
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bool SlowVMLx;
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/// SlowFPBrcc - True if floating point compare + branch is slow.
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bool SlowFPBrcc;
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/// IsThumb - True if we are in thumb mode, false if in ARM mode.
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bool IsThumb;
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@ -133,6 +136,7 @@ protected:
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bool hasDivide() const { return HasHardwareDivide; }
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bool hasT2ExtractPack() const { return HasT2ExtractPack; }
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bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
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bool isFPBrccSlow() const { return SlowFPBrcc; }
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bool hasFP16() const { return HasFP16; }
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