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Configure the asmwriter to allow constant pools to be printed correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24841 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,6 +40,8 @@ namespace {
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Data32bitsDirective = "\t.word\t";
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Data64bitsDirective = "\t.xword\t";
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ZeroDirective = 0; // no .zero or .space!
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CommentString = "!";
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ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
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}
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/// We name each basic block in a Function with a unique number, so
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@ -715,7 +715,6 @@ def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
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def : Pat<(retflag ICC/*HACK*/), (RETL)>;
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// Map integer extload's to zextloads.
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// Handling 1 bit extload
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def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
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def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
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def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
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@ -40,6 +40,8 @@ namespace {
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Data32bitsDirective = "\t.word\t";
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Data64bitsDirective = "\t.xword\t";
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ZeroDirective = 0; // no .zero or .space!
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CommentString = "!";
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ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
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}
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/// We name each basic block in a Function with a unique number, so
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@ -715,7 +715,6 @@ def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
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def : Pat<(retflag ICC/*HACK*/), (RETL)>;
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// Map integer extload's to zextloads.
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// Handling 1 bit extload
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def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
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def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
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def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
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