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https://github.com/c64scene-ar/llvm-6502.git
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Attemt to provide correct encodings for Thumb2 binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118939 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
893d7fe209
commit
7a6b810dcb
@ -170,7 +170,7 @@ def t2addrmode_so_reg : Operand<i32>,
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// Multiclass helpers...
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//
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class T2TwoRegShiftedImm<dag oops, dag iops, InstrItinClass itin,
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class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2sI<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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@ -262,9 +262,10 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Commutable = 0, string wide = ""> {
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// shifted imm
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def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), iii,
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opc, "\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
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def ri : T2TwoRegImm<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
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opc, "\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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@ -272,9 +273,10 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
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let Inst{15} = 0;
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}
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// register
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def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), iir,
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opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
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[(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
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def rr : T2ThreeReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
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opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
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[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
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let isCommutable = Commutable;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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@ -285,9 +287,10 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), iis,
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opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
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[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
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def rs : T2TwoRegShiftedReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
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opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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@ -307,9 +310,10 @@ multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
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/// it is equivalent to the T2I_bin_irs counterpart.
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multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
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opc, ".w\t$dst, $rhs, $lhs",
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[(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
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def ri : T2TwoRegImm<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
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opc, ".w\t$Rd, $imm, $Rn",
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[(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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@ -317,8 +321,8 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
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let Inst{15} = 0;
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}
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// register
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def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
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opc, "\t$dst, $rhs, $lhs",
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def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
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opc, "\t$Rd, $Rm, $Rn",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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@ -329,9 +333,10 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsir,
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opc, "\t$dst, $rhs, $lhs",
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[(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
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def rs : T2TwoRegShiftedReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
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IIC_iALUsir, opc, "\t$Rd, $ShiftedRm, $Rn",
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[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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@ -346,9 +351,9 @@ multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Commutable = 0> {
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// shifted imm
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def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), iii,
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!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
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def ri : T2TwoRegImm<(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
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!strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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@ -356,9 +361,9 @@ multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
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let Inst{15} = 0;
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}
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// register
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def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), iir,
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!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
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def rr : T2ThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
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!strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
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let isCommutable = Commutable;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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@ -369,9 +374,10 @@ multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), iis,
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!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
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def rs : T2TwoRegShiftedReg<
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(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
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!strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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@ -388,9 +394,10 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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// The register-immediate version is re-materializable. This is useful
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// in particular for taking the address of a local.
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let isReMaterializable = 1 in {
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def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
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opc, ".w\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
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def ri : T2TwoRegImm<
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(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
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opc, ".w\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24} = 1;
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@ -400,9 +407,10 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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}
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}
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// 12-bit imm
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def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
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!strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
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def ri12 : T2TwoRegImm<
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(outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
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!strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 1;
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let Inst{24} = 0;
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@ -411,9 +419,9 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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let Inst{15} = 0;
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}
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// register
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def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
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opc, ".w\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
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def rr : T2ThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
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opc, ".w\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
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let isCommutable = Commutable;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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@ -425,9 +433,10 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
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opc, ".w\t$dst, $lhs, $rhs",
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[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
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def rs : T2TwoRegShiftedReg<
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(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
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IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24} = 1;
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@ -443,7 +452,7 @@ let Uses = [CPSR] in {
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multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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// shifted imm
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def ri : T2TwoRegShiftedImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
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def ri : T2TwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
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IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
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Requires<[IsThumb2]> {
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@ -485,7 +494,7 @@ let Defs = [CPSR] in {
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multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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// shifted imm
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def ri : T2TwoRegShiftedImm<
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def ri : T2TwoRegImm<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
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opc, "\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
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@ -530,9 +539,10 @@ multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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let Defs = [CPSR] in {
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multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
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!strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
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[(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
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def ri : T2TwoRegImm<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
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!strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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@ -540,9 +550,10 @@ multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
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let Inst{15} = 0;
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}
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// shifted register
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def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
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!strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
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[(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
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def rs : T2TwoRegShiftedReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
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IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
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[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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@ -874,17 +885,19 @@ def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
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}
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// ADD r, sp, {so_imm|i12}
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def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
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IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
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def t2ADDrSPi : T2TwoRegImm<
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(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
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IIC_iALUi, "add", ".w\t$Rn, $Rn, $imm", []> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = 0b1000;
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let Inst{20} = ?; // The S bit.
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let Inst{19-16} = 0b1101; // Rn = sp
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let Inst{19-16} = 0b1101;
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let Inst{15} = 0;
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}
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def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
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IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
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def t2ADDrSPi12 : T2TwoRegImm<
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(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
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IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 1;
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let Inst{24-21} = 0b0000;
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