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PR5207: Rename overloaded APInt methods set(), clear(), flip() to

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setAllBits(), setBit(unsigned), etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jay Foad
2010-12-01 08:53:58 +00:00
parent ce2b68fb54
commit 7a874ddda0
11 changed files with 66 additions and 66 deletions
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36
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@ -121,13 +121,13 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
}
if (isa<ConstantPointerNull>(V)) {
// We know all of the bits for a constant!
KnownOne.clear();
KnownOne.clearAllBits();
KnownZero = DemandedMask;
return 0;
}
KnownZero.clear();
KnownOne.clear();
KnownZero.clearAllBits();
KnownOne.clearAllBits();
if (DemandedMask == 0) { // Not demanding any bits from V.
if (isa<UndefValue>(V))
return 0;
@ -451,7 +451,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If any of the sign extended bits are demanded, we know that the sign
// bit is demanded.
if ((NewBits & DemandedMask) != 0)
InputDemandedBits.set(SrcBitWidth-1);
InputDemandedBits.setBit(SrcBitWidth-1);
InputDemandedBits.trunc(SrcBitWidth);
KnownZero.trunc(SrcBitWidth);
@ -634,7 +634,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If any of the "high bits" are demanded, we should set the sign bit as
// demanded.
if (DemandedMask.countLeadingZeros() <= ShiftAmt)
DemandedMaskIn.set(BitWidth-1);
DemandedMaskIn.setBit(BitWidth-1);
if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
KnownZero, KnownOne, Depth+1))
return I;
@ -793,10 +793,10 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
for (unsigned i = 0; i != VWidth; ++i)
if (!DemandedElts[i]) { // If not demanded, set to undef.
Elts.push_back(Undef);
UndefElts.set(i);
UndefElts.setBit(i);
} else if (isa<UndefValue>(CV->getOperand(i))) { // Already undef.
Elts.push_back(Undef);
UndefElts.set(i);
UndefElts.setBit(i);
} else { // Otherwise, defined.
Elts.push_back(CV->getOperand(i));
}
@ -879,13 +879,13 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
// Otherwise, the element inserted overwrites whatever was there, so the
// input demanded set is simpler than the output set.
APInt DemandedElts2 = DemandedElts;
DemandedElts2.clear(IdxNo);
DemandedElts2.clearBit(IdxNo);
TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2,
UndefElts, Depth+1);
if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
// The inserted element is defined.
UndefElts.clear(IdxNo);
UndefElts.clearBit(IdxNo);
break;
}
case Instruction::ShuffleVector: {
@ -900,9 +900,9 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
assert(MaskVal < LHSVWidth * 2 &&
"shufflevector mask index out of range!");
if (MaskVal < LHSVWidth)
LeftDemanded.set(MaskVal);
LeftDemanded.setBit(MaskVal);
else
RightDemanded.set(MaskVal - LHSVWidth);
RightDemanded.setBit(MaskVal - LHSVWidth);
}
}
}
@ -921,16 +921,16 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
for (unsigned i = 0; i < VWidth; i++) {
unsigned MaskVal = Shuffle->getMaskValue(i);
if (MaskVal == -1u) {
UndefElts.set(i);
UndefElts.setBit(i);
} else if (MaskVal < LHSVWidth) {
if (UndefElts4[MaskVal]) {
NewUndefElts = true;
UndefElts.set(i);
UndefElts.setBit(i);
}
} else {
if (UndefElts3[MaskVal - LHSVWidth]) {
NewUndefElts = true;
UndefElts.set(i);
UndefElts.setBit(i);
}
}
}
@ -973,7 +973,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
Ratio = VWidth/InVWidth;
for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
if (DemandedElts[OutIdx])
InputDemandedElts.set(OutIdx/Ratio);
InputDemandedElts.setBit(OutIdx/Ratio);
}
} else {
// Untested so far.
@ -985,7 +985,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
Ratio = InVWidth/VWidth;
for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
if (DemandedElts[InIdx/Ratio])
InputDemandedElts.set(InIdx);
InputDemandedElts.setBit(InIdx);
}
// div/rem demand all inputs, because they don't want divide by zero.
@ -1004,7 +1004,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
// undef.
for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
if (UndefElts2[OutIdx/Ratio])
UndefElts.set(OutIdx);
UndefElts.setBit(OutIdx);
} else if (VWidth < InVWidth) {
llvm_unreachable("Unimp");
// If there are more elements in the source than there are in the result,
@ -1013,7 +1013,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
UndefElts = ~0ULL >> (64-VWidth); // Start out all undef.
for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
if (!UndefElts2[InIdx]) // Not undef?
UndefElts.clear(InIdx/Ratio); // Clear undef bit.
UndefElts.clearBit(InIdx/Ratio); // Clear undef bit.
}
break;
}