From 7ab54047e7bdde3e57a3c9af2c88fb13bb950f44 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 21 Mar 2006 07:18:26 +0000
Subject: [PATCH] Combine 2 entries

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26921 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/README.txt | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt
index d9aaecbb96d..4972818dbf5 100644
--- a/lib/Target/X86/README.txt
+++ b/lib/Target/X86/README.txt
@@ -485,6 +485,12 @@ This will be solved when we go to a dynamic programming based isel.
 
 //===---------------------------------------------------------------------===//
 
+Should generate min/max for stuff like:
+
+void minf(float a, float b, float *X) {
+  *X = a <= b ? a : b;
+}
+
 Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
 and ISD::FMAX node types?
 
@@ -636,13 +642,5 @@ lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
 
 //===---------------------------------------------------------------------===//
 
-Should generate min/max for stuff like:
-
-void minf(float a, float b, float *X) {
-  *X = a <= b ? a : b;
-}
-
-//===---------------------------------------------------------------------===//
-
 Teach the coallescer to coales vregs of different register classes. e.g. FR32 /
 FR64 to VR128.