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[mips] Set isAllocatable bit of unallocatable register classes to 0.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-03-14 23:09:19 +00:00
parent 157c6c4e8e
commit 7abc88bc83
1 changed files with 13 additions and 8 deletions
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21
lib/Target/Mips/MipsRegisterInfo.td
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@ -18,6 +18,10 @@ def sub_lo : SubRegIndex;
def sub_hi : SubRegIndex; def sub_hi : SubRegIndex;
} }
class Unallocatable {
bit isAllocatable = 0;
}
// We have banks of 32 registers each. // We have banks of 32 registers each.
class MipsReg<bits<16> Enc, string n> : Register<n> { class MipsReg<bits<16> Enc, string n> : Register<n> {
let HWEncoding = Enc; let HWEncoding = Enc;
@ -291,9 +295,9 @@ def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
// Callee save // Callee save
S0, S1)>; S0, S1)>;
def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>; def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>; def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
// 64bit fp: // 64bit fp:
// * FGR64 - 32 64-bit registers // * FGR64 - 32 64-bit registers
@ -319,18 +323,19 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
// Condition Register for floating point operations // Condition Register for floating point operations
def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>; def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
// Hi/Lo Registers // Hi/Lo Registers
def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>, Unallocatable;
def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>, Unallocatable;
// Hardware registers // Hardware registers
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>; def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable;
// Accumulator Registers // Accumulator Registers
def ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>; def ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>,
Unallocatable;
def CPURegsAsmOperand : AsmOperandClass { def CPURegsAsmOperand : AsmOperandClass {
let Name = "CPURegsAsm"; let Name = "CPURegsAsm";