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Simplify extract element of a scalar to vector.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62383 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2009-01-17 00:07:25 +00:00
parent de62aeaec4
commit 7ac9cdfc99
2 changed files with 26 additions and 5 deletions
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18
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4878,16 +4878,24 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
}
SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
// (vextract (scalar_to_vector val, 0) -> val
SDValue InVec = N->getOperand(0);
SDValue EltNo = N->getOperand(1);
if (isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && Elt == 0) {
return InVec.getOperand(0);
}
}
// Perform only after legalization to ensure build_vector / vector_shuffle
// optimizations have already been done.
if (!LegalOperations) return SDValue();
SDValue InVec = N->getOperand(0);
SDValue EltNo = N->getOperand(1);
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
if (isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();

13
test/CodeGen/X86/scalar-extract.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx -o %t -f
; RUN: not grep movq %t
; Check that widening doesn't introduce a mmx register in this case when
; a simple load/store would suffice.
define void @foo(<2 x i16>* %A, <2 x i16>* %B) {
entry:
%tmp1 = load <2 x i16>* %A ; <<2 x i16>> [#uses=1]
store <2 x i16> %tmp1, <2 x i16>* %B
ret void
}