mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Commute x86 cmove instructions by swapping the operands and change the condition
to its inverse. Testing this as llcbeta git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42661 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
57cce6c466
commit
7ad42d9ec0
@ -22,8 +22,15 @@
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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namespace {
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cl::opt<bool>
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EnableCommuteCMove("enable-x86-commute-cmove",
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cl::desc("Commute conditional moves by inverting conditions"));
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}
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X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
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TM(tm), RI(tm, *this) {
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@ -366,7 +373,6 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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/// commute them.
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///
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MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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// FIXME: Can commute cmoves by changing the condition!
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switch (MI->getOpcode()) {
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case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
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case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
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@ -394,6 +400,100 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
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.addReg(B, false, false, BisKill).addImm(Size-Amt);
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}
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case X86::CMOVB16rr:
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case X86::CMOVB32rr:
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case X86::CMOVB64rr:
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case X86::CMOVAE16rr:
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case X86::CMOVAE32rr:
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case X86::CMOVAE64rr:
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case X86::CMOVE16rr:
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case X86::CMOVE32rr:
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case X86::CMOVE64rr:
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case X86::CMOVNE16rr:
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case X86::CMOVNE32rr:
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case X86::CMOVNE64rr:
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case X86::CMOVBE16rr:
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case X86::CMOVBE32rr:
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case X86::CMOVBE64rr:
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case X86::CMOVA16rr:
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case X86::CMOVA32rr:
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case X86::CMOVA64rr:
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case X86::CMOVL16rr:
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case X86::CMOVL32rr:
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case X86::CMOVL64rr:
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case X86::CMOVGE16rr:
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case X86::CMOVGE32rr:
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case X86::CMOVGE64rr:
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case X86::CMOVLE16rr:
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case X86::CMOVLE32rr:
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case X86::CMOVLE64rr:
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case X86::CMOVG16rr:
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case X86::CMOVG32rr:
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case X86::CMOVG64rr:
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case X86::CMOVS16rr:
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case X86::CMOVS32rr:
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case X86::CMOVS64rr:
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case X86::CMOVNS16rr:
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case X86::CMOVNS32rr:
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case X86::CMOVNS64rr:
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case X86::CMOVP16rr:
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case X86::CMOVP32rr:
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case X86::CMOVP64rr:
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case X86::CMOVNP16rr:
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case X86::CMOVNP32rr:
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case X86::CMOVNP64rr: {
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if (!EnableCommuteCMove)
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return 0;
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unsigned Opc = 0;
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switch (MI->getOpcode()) {
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default: break;
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case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
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case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
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case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
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case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
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case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
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case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
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case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
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case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
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case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
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case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
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case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
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case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
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case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
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case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
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case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
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case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
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case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
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case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
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case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
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case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
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case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
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case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
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case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
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case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
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case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
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case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
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case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
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case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
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case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
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case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
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case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
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case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
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case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
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case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
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case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
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case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
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case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
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case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
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case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
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case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
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case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
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case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
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}
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MI->setInstrDescriptor(get(Opc));
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// Fallthrough intended.
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}
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default:
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return TargetInstrInfo::commuteInstruction(MI);
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}
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@ -647,30 +647,19 @@ let isTwoAddress = 1 in {
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// Conditional moves
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let Uses = [EFLAGS] in {
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let isCommutable = 1 in {
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def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovb\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_B, EFLAGS))]>,
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TB, OpSize;
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def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovb\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_B, EFLAGS))]>,
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TB, OpSize;
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def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovb\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_B, EFLAGS))]>,
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TB;
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def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovb\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_B, EFLAGS))]>,
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TB;
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def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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@ -678,324 +667,327 @@ def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_AE, EFLAGS))]>,
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TB, OpSize;
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def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovae\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_AE, EFLAGS))]>,
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TB, OpSize;
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def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovae\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_AE, EFLAGS))]>,
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TB;
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def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovae\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_AE, EFLAGS))]>,
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TB;
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def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmove\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_E, EFLAGS))]>,
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TB, OpSize;
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def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmove\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_E, EFLAGS))]>,
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TB, OpSize;
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def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmove\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_E, EFLAGS))]>,
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TB;
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def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmove\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_E, EFLAGS))]>,
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TB;
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def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovne\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_NE, EFLAGS))]>,
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TB, OpSize;
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def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovne\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_NE, EFLAGS))]>,
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TB, OpSize;
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def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovne\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_NE, EFLAGS))]>,
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TB;
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def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovne\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_NE, EFLAGS))]>,
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TB;
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def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovbe\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_BE, EFLAGS))]>,
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TB, OpSize;
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def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovbe\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_BE, EFLAGS))]>,
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TB, OpSize;
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def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovbe\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_BE, EFLAGS))]>,
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TB;
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def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovbe\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_BE, EFLAGS))]>,
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TB;
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def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmova\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_A, EFLAGS))]>,
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TB, OpSize;
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def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmova\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_A, EFLAGS))]>,
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TB, OpSize;
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def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmova\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_A, EFLAGS))]>,
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TB;
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def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmova\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_A, EFLAGS))]>,
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TB;
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def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovl\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_L, EFLAGS))]>,
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TB, OpSize;
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def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovl\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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X86_COND_L, EFLAGS))]>,
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TB, OpSize;
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def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"cmovl\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
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X86_COND_L, EFLAGS))]>,
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TB;
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def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
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(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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"cmovl\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_L, EFLAGS))]>,
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TB;
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def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovge\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
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X86_COND_GE, EFLAGS))]>,
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TB, OpSize;
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def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
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(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
||||
X86_COND_GE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>,
|
||||
TB;
|
||||
|
||||
def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB;
|
||||
|
||||
def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB;
|
||||
|
||||
def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB;
|
||||
|
||||
def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB;
|
||||
|
||||
def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB;
|
||||
|
||||
def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
|
||||
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
||||
X86_COND_NP, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NP, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
|
||||
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
||||
X86_COND_NP, EFLAGS))]>,
|
||||
TB;
|
||||
} // isCommutable = 1
|
||||
|
||||
def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_NP, EFLAGS))]>,
|
||||
TB;
|
||||
|
||||
def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_B, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_B, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_AE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_AE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_E, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_E, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_NE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_BE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_BE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_A, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_A, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_L, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_L, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
|
||||
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>,
|
||||
TB;
|
||||
def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
|
||||
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
X86_COND_NP, EFLAGS))]>,
|
||||
TB, OpSize;
|
||||
} // Uses = [EFLAGS]
|
||||
|
||||
|
||||
|
||||
@ -778,141 +778,144 @@ def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
|
||||
// Conditional moves
|
||||
let Uses = [EFLAGS], isTwoAddress = 1 in {
|
||||
let isCommutable = 1 in {
|
||||
def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_BE, EFLAGS))]>, TB;
|
||||
def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_BE, EFLAGS))]>, TB;
|
||||
def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NP, EFLAGS))]>, TB;
|
||||
} // isCommutable = 1
|
||||
|
||||
def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_BE, EFLAGS))]>, TB;
|
||||
def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user