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During post-legalization DAG combining, be careful to only create shifts where the RHS is of the legal type for the new operation.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129484 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-04-13 23:22:23 +00:00
parent e8d087ad35
commit 7adf862eb2
1 changed files with 8 additions and 1 deletions
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9
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1678,6 +1678,13 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
if (!ShAmt)
break;
SDValue Shift = In.getOperand(1);
if (TLO.LegalTypes()) {
uint64_t ShVal = ShAmt->getZExtValue();
Shift =
TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
}
APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
OperandBitWidth - BitWidth);
HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
@ -1691,7 +1698,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
Op.getValueType(),
NewTrunc,
In.getOperand(1)));
Shift));
}
break;
}