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Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introduced most of these recently.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-04-30 07:17:30 +00:00
parent ddbde80aae
commit 7ae9b5fc71
13 changed files with 37 additions and 44 deletions
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4
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -1563,7 +1563,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
Hi = DAG.getNode(ISD::ADD, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
ISD::SETULT);
SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
@ -1576,7 +1576,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
} else {
Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
Hi = DAG.getNode(ISD::SUB, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
SDValue Cmp =
DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
LoOps[0], LoOps[1], ISD::SETULT);

2
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
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@ -355,7 +355,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
IntegerToVector(N->getOperand(0), NumElts, Ops, NVT.getVectorElementType());
SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
ArrayRef<SDValue>(&Ops[0], NumElts));
makeArrayRef(Ops.data(), NumElts));
return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), Vec);
}

7
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -1745,7 +1745,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
ConcatOps[j] = UndefVal;
}
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
ArrayRef<SDValue>(&ConcatOps[0], NumOps));
makeArrayRef(ConcatOps.data(), NumOps));
}
SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
@ -2724,8 +2724,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
if (NewLdTy != LdTy) {
// Create a larger vector
ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
ArrayRef<SDValue>(&ConcatOps[Idx],
End - Idx));
makeArrayRef(&ConcatOps[Idx], End - Idx));
Idx = End - 1;
LdTy = NewLdTy;
}
@ -2734,7 +2733,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
ArrayRef<SDValue>(&ConcatOps[Idx], End - Idx));
makeArrayRef(&ConcatOps[Idx], End - Idx));
// We need to fill the rest with undefs to build the vector
unsigned NumOps = WidenWidth / LdTy.getSizeInBits();

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -527,7 +527,7 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
// Add the return value info.
AddNodeIDValueTypes(ID, N->getVTList());
// Add the operand info.
AddNodeIDOperands(ID, ArrayRef<SDUse>(N->op_begin(), N->op_end()));
AddNodeIDOperands(ID, makeArrayRef(N->op_begin(), N->op_end()));
// Handle SDNode leafs with special info.
AddNodeIDCustom(ID, N);

11
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -3480,7 +3480,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
if (ChainI == MaxParallelChains) {
assert(PendingLoads.empty() && "PendingLoads must be serialized first");
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
ArrayRef<SDValue>(Chains.data(), ChainI));
makeArrayRef(Chains.data(), ChainI));
Root = Chain;
ChainI = 0;
}
@ -3498,7 +3498,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
if (!ConstantMemory) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
ArrayRef<SDValue>(Chains.data(), ChainI));
makeArrayRef(Chains.data(), ChainI));
if (isVolatile)
DAG.setRoot(Chain);
else
@ -3543,7 +3543,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
// See visitLoad comments.
if (ChainI == MaxParallelChains) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
ArrayRef<SDValue>(Chains.data(), ChainI));
makeArrayRef(Chains.data(), ChainI));
Root = Chain;
ChainI = 0;
}
@ -3557,7 +3557,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
}
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
ArrayRef<SDValue>(Chains.data(), ChainI));
makeArrayRef(Chains.data(), ChainI));
DAG.setRoot(StoreNode);
}
@ -7496,8 +7496,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
SDValue Res = DAG.getMergeValues(ArrayRef<SDValue>(ArgValues.data(),
NumValues),
SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
SDB->getCurSDLoc());
SDB->setValue(I, Res);

8
lib/Target/ARM/ARMSelectionDAGInfo.cpp
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@ -73,7 +73,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
SrcOff += VTSize;
}
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
ArrayRef<SDValue>(TFOps, i));
makeArrayRef(TFOps, i));
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
@ -85,7 +85,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
DstOff += VTSize;
}
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
ArrayRef<SDValue>(TFOps, i));
makeArrayRef(TFOps, i));
EmittedNumMemOps += i;
}
@ -116,7 +116,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
BytesLeft -= VTSize;
}
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
ArrayRef<SDValue>(TFOps, i));
makeArrayRef(TFOps, i));
i = 0;
BytesLeft = BytesLeftSave;
@ -138,7 +138,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
BytesLeft -= VTSize;
}
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
ArrayRef<SDValue>(TFOps, i));
makeArrayRef(TFOps, i));
}
// Adjust parameters for memset, EABI uses format (ptr, size, value),

6
lib/Target/ARM64/ARM64ISelLowering.cpp
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@ -4358,7 +4358,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
makeArrayRef(TBLMask.data(), IndexLen)));
} else {
if (IndexLen == 8) {
V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
@ -4366,7 +4366,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
makeArrayRef(TBLMask.data(), IndexLen)));
} else {
// FIXME: We cannot, for the moment, emit a TBL2 instruction because we
// cannot currently represent the register constraints on the input
@ -4378,7 +4378,7 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
DAG.getConstant(Intrinsic::arm64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
makeArrayRef(TBLMask.data(), IndexLen)));
}
}
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);

8
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -489,7 +489,7 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
Op0->getVTList(),
ArrayRef<SDValue>(Ops, Op0->getNumOperands()));
makeArrayRef(Ops, Op0->getNumOperands()));
return Op0;
}
}
@ -834,7 +834,7 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
Op0Op0->getOperand(2) };
DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
Op0Op0->getVTList(),
ArrayRef<SDValue>(Ops, Op0Op0->getNumOperands()));
makeArrayRef(Ops, Op0Op0->getNumOperands()));
return Op0Op0;
}
}
@ -1284,7 +1284,7 @@ static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
if (ViaVecTy != ResVecTy)
Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
@ -1324,7 +1324,7 @@ static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
SplatValueA, SplatValueB, SplatValueA, SplatValueB };
SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
if (VecTy != ViaVecTy)
Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);

9
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
View File

@ -1084,8 +1084,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
}
SDValue Ops[] = { Addr, Chain };
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
ArrayRef<SDValue>(Ops, 2));
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
} else if (Subtarget.is64Bit()
? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
: SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
@ -1271,8 +1270,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
SDValue Ops[] = { Base, Offset, Chain };
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
ArrayRef<SDValue>(Ops, 3));
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
} else {
if (Subtarget.is64Bit()) {
switch (N->getOpcode()) {
@ -1455,8 +1453,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
}
SDValue Ops[] = { Op1, Chain };
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
ArrayRef<SDValue>(Ops, 2));
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
}
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);

9
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -3474,7 +3474,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
// descriptor.
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
Chain = LoadFuncPtr.getValue(1);
InFlag = LoadFuncPtr.getValue(2);
@ -3511,7 +3511,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
}
Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
InFlag = Chain.getValue(1);
NodeTys.clear();
@ -3940,8 +3940,7 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
SDValue Ops[] = { Chain, InFlag };
Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
dl, VTs,
ArrayRef<SDValue>(Ops, InFlag.getNode() ? 2 : 1));
dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
InFlag = Chain.getValue(1);
}
@ -5282,7 +5281,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
MVT::f64, // return register
MVT::Glue // unused in this context
};
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, ArrayRef<SDValue>());
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
// Save FP register to stack slot
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);

2
lib/Target/R600/R600ISelLowering.cpp
View File

@ -1280,7 +1280,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
NumElements = VT.getVectorNumElements();
}
Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
ArrayRef<SDValue>(Slots, NumElements));
makeArrayRef(Slots, NumElements));
} else {
// non-constant ptr can't be folded, keeps it as a v4f32 load
Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,

4
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -772,8 +772,8 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
}
// Join the stores, which are independent of one another.
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
ArrayRef<SDValue>(&MemOps[NumFixedFPRs],
SystemZ::NumArgFPRs-NumFixedFPRs));
makeArrayRef(&MemOps[NumFixedFPRs],
SystemZ::NumArgFPRs-NumFixedFPRs));
}
}

9
lib/Target/X86/X86ISelLowering.cpp
View File

@ -85,8 +85,8 @@ static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
// If the input is a buildvector just emit a smaller one.
if (Vec.getOpcode() == ISD::BUILD_VECTOR)
return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
ArrayRef<SDUse>(Vec->op_begin()+NormalizedIdxVal,
ElemsPerChunk));
makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
ElemsPerChunk));
SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
@ -6140,10 +6140,9 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
// Build both the lower and upper subvector.
SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
ArrayRef<SDValue>(&V[0], NumElems/2));
makeArrayRef(&V[0], NumElems/2));
SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
ArrayRef<SDValue>(&V[NumElems / 2],
NumElems/2));
makeArrayRef(&V[NumElems / 2], NumElems/2));
// Recreate the wider vector with the lower and upper part.
if (VT.is256BitVector())