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Added a handful of x86-32 instructions that were missing so that llvm-mc would

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be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby
2010-10-18 17:04:36 +00:00
parent 9edab3a9e1
commit 7aef62ff8c
5 changed files with 123 additions and 0 deletions
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5
lib/Target/X86/X86InstrControl.td
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@@ -24,10 +24,15 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"ret\t$amt",
[(X86retflag timm:$amt)]>;
def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"retw\t$amt",
[(X86retflag timm:$amt)]>, OpSize;
def LRET : I <0xCB, RawFrm, (outs), (ins),
"lret", []>;
def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
"lret\t$amt", []>;
def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
"lretw\t$amt", []>, OpSize;
}
// Unconditional branches.