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Slightly change TableGen's definition of a register subclass.
A subclass is allowed to have a larger spill size than the superclass, and the spill alignment must be a multiple of the superclass alignment. This causes the following new subclass relations: === Alpha === F4RC -> F8RC === PPC === F4RC -> F8RC === SPU === R8C -> R16C -> R32C/R32FP -> R64C/R64FP -> GPRC/VECREG === X86 === FR32 -> FR64 -> VR128 RFP32 -> RFP64 -> RFP80 These subclass relations are consistent with the behaviour of -join-cross-class-copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70511 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -340,8 +340,21 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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bool Empty = true;
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for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
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// RC2 is a sub-class of RC if it is a valid replacement for any
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// instruction operand where an RC register is required. It must satisfy
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// these conditions:
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//
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// 1. All RC2 registers are also in RC.
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// 2. The RC2 spill size must not be smaller that the RC spill size.
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// 3. RC2 spill alignment must be compatible with RC.
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//
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// Sub-classes are used to determine if a virtual register can be used
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// as an instruction operand, or if it must be copied first.
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if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
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RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
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(RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
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RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
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continue;
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if (!Empty) OS << ", ";
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