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Add some simple integer patterns. This allows us to compile this:
int %test(int %A) { %B = add int %A, 1 %C = xor int %B, 123 ret int %C } into this: test: save -96, %sp, %sp add %i0, 1, %l0 xor %l0, 123, %i0 restore %g0, %g0, %g0 retl nop for example. I guess it would make sense to add reg/reg versions too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24774 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -30,6 +30,15 @@ class InstV8 : Instruction { // SparcV8 instruction baseline
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include "SparcV8InstrFormats.td"
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def simm13 : PatLeaf<(imm), [{
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// simm13 predicate - True if the imm fits in a 13-bit sign extended field.
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return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
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}]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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// Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -164,7 +173,8 @@ def ANDrr : F3_1<2, 0b000001,
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"and $b, $c, $dst">;
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"and $b, $c, $dst">;
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def ANDri : F3_2<2, 0b000001,
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def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"and $b, $c, $dst", []>;
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"and $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
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def ANDCCrr : F3_1<2, 0b010001,
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def ANDCCrr : F3_1<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andcc $b, $c, $dst">;
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"andcc $b, $c, $dst">;
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@ -188,7 +198,8 @@ def ORrr : F3_1<2, 0b000010,
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"or $b, $c, $dst">;
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"or $b, $c, $dst">;
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def ORri : F3_2<2, 0b000010,
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def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"or $b, $c, $dst", []>;
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"or $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
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def ORCCrr : F3_1<2, 0b010010,
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def ORCCrr : F3_1<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orcc $b, $c, $dst">;
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"orcc $b, $c, $dst">;
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@ -212,7 +223,8 @@ def XORrr : F3_1<2, 0b000011,
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"xor $b, $c, $dst">;
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"xor $b, $c, $dst">;
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def XORri : F3_2<2, 0b000011,
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def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xor $b, $c, $dst", []>;
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"xor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
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def XORCCrr : F3_1<2, 0b010011,
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def XORCCrr : F3_1<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xorcc $b, $c, $dst">;
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"xorcc $b, $c, $dst">;
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@ -258,7 +270,8 @@ def ADDrr : F3_1<2, 0b000000,
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"add $b, $c, $dst">;
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"add $b, $c, $dst">;
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def ADDri : F3_2<2, 0b000000,
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def ADDri : F3_2<2, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"add $b, $c, $dst", []>;
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"add $b, $c, $dst",
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[(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
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def ADDCCrr : F3_1<2, 0b010000,
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def ADDCCrr : F3_1<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addcc $b, $c, $dst">;
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"addcc $b, $c, $dst">;
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@ -284,7 +297,8 @@ def SUBrr : F3_1<2, 0b000100,
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"sub $b, $c, $dst">;
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"sub $b, $c, $dst">;
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def SUBri : F3_2<2, 0b000100,
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def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sub $b, $c, $dst", []>;
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"sub $b, $c, $dst",
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[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
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def SUBCCrr : F3_1<2, 0b010100,
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst">;
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"subcc $b, $c, $dst">;
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@ -30,6 +30,15 @@ class InstV8 : Instruction { // SparcV8 instruction baseline
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include "SparcV8InstrFormats.td"
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def simm13 : PatLeaf<(imm), [{
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// simm13 predicate - True if the imm fits in a 13-bit sign extended field.
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return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
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}]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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// Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -164,7 +173,8 @@ def ANDrr : F3_1<2, 0b000001,
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"and $b, $c, $dst">;
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"and $b, $c, $dst">;
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def ANDri : F3_2<2, 0b000001,
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def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"and $b, $c, $dst", []>;
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"and $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
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def ANDCCrr : F3_1<2, 0b010001,
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def ANDCCrr : F3_1<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andcc $b, $c, $dst">;
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"andcc $b, $c, $dst">;
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@ -188,7 +198,8 @@ def ORrr : F3_1<2, 0b000010,
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"or $b, $c, $dst">;
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"or $b, $c, $dst">;
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def ORri : F3_2<2, 0b000010,
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def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"or $b, $c, $dst", []>;
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"or $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
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def ORCCrr : F3_1<2, 0b010010,
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def ORCCrr : F3_1<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orcc $b, $c, $dst">;
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"orcc $b, $c, $dst">;
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@ -212,7 +223,8 @@ def XORrr : F3_1<2, 0b000011,
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"xor $b, $c, $dst">;
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"xor $b, $c, $dst">;
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def XORri : F3_2<2, 0b000011,
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def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xor $b, $c, $dst", []>;
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"xor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
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def XORCCrr : F3_1<2, 0b010011,
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def XORCCrr : F3_1<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xorcc $b, $c, $dst">;
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"xorcc $b, $c, $dst">;
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@ -258,7 +270,8 @@ def ADDrr : F3_1<2, 0b000000,
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"add $b, $c, $dst">;
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"add $b, $c, $dst">;
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def ADDri : F3_2<2, 0b000000,
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def ADDri : F3_2<2, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"add $b, $c, $dst", []>;
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"add $b, $c, $dst",
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[(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
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def ADDCCrr : F3_1<2, 0b010000,
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def ADDCCrr : F3_1<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addcc $b, $c, $dst">;
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"addcc $b, $c, $dst">;
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@ -284,7 +297,8 @@ def SUBrr : F3_1<2, 0b000100,
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"sub $b, $c, $dst">;
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"sub $b, $c, $dst">;
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def SUBri : F3_2<2, 0b000100,
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def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sub $b, $c, $dst", []>;
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"sub $b, $c, $dst",
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[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
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def SUBCCrr : F3_1<2, 0b010100,
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst">;
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"subcc $b, $c, $dst">;
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