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https://github.com/c64scene-ar/llvm-6502.git
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Add missing builtins to the PPC back end for ABI compliance (vol. 1)
This patch corresponds to review: http://reviews.llvm.org/D10638 This is the back end portion of patch http://reviews.llvm.org/D10637 It just adds the code gen and intrinsic functions necessary to support that patch to the back end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240820 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic
parent
a5d25f61ae
commit
7b3cde87f1
@ -687,6 +687,32 @@ def int_ppc_vsx_xsmindp : PowerPC_VSX_Sca_DDD_Intrinsic<"xsmindp">;
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// Vector divide.
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// Vector divide.
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def int_ppc_vsx_xvdivdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvdivdp">;
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def int_ppc_vsx_xvdivdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvdivdp">;
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def int_ppc_vsx_xvdivsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvdivsp">;
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def int_ppc_vsx_xvdivsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvdivsp">;
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// Vector round-to-infinity (ceil)
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def int_ppc_vsx_xvrspip :
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvrdpip :
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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// Vector compare
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def int_ppc_vsx_xvcmpeqdp :
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PowerPC_VSX_Intrinsic<"xvcmpeqdp", [llvm_v2i64_ty],
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[llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcmpeqsp :
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PowerPC_VSX_Intrinsic<"xvcmpeqsp", [llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcmpgedp :
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PowerPC_VSX_Intrinsic<"xvcmpgedp", [llvm_v2i64_ty],
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[llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcmpgesp :
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PowerPC_VSX_Intrinsic<"xvcmpgesp", [llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcmpgtdp :
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PowerPC_VSX_Intrinsic<"xvcmpgtdp", [llvm_v2i64_ty],
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[llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcmpgtsp :
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PowerPC_VSX_Intrinsic<"xvcmpgtsp", [llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -457,22 +457,34 @@ let Uses = [RM] in {
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defm XVCMPEQDP : XX3Form_Rcr<60, 99,
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defm XVCMPEQDP : XX3Form_Rcr<60, 99,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
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[(set v2i64:$XT,
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(int_ppc_vsx_xvcmpeqdp v2f64:$XA, v2f64:$XB))]>;
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defm XVCMPEQSP : XX3Form_Rcr<60, 67,
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defm XVCMPEQSP : XX3Form_Rcr<60, 67,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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"xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,
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[(set v4i32:$XT,
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(int_ppc_vsx_xvcmpeqsp v4f32:$XA, v4f32:$XB))]>;
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defm XVCMPGEDP : XX3Form_Rcr<60, 115,
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defm XVCMPGEDP : XX3Form_Rcr<60, 115,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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"xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare,
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[(set v2i64:$XT,
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(int_ppc_vsx_xvcmpgedp v2f64:$XA, v2f64:$XB))]>;
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defm XVCMPGESP : XX3Form_Rcr<60, 83,
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defm XVCMPGESP : XX3Form_Rcr<60, 83,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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"xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare,
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[(set v4i32:$XT,
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(int_ppc_vsx_xvcmpgesp v4f32:$XA, v4f32:$XB))]>;
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defm XVCMPGTDP : XX3Form_Rcr<60, 107,
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defm XVCMPGTDP : XX3Form_Rcr<60, 107,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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"xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare,
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[(set v2i64:$XT,
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(int_ppc_vsx_xvcmpgtdp v2f64:$XA, v2f64:$XB))]>;
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defm XVCMPGTSP : XX3Form_Rcr<60, 75,
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defm XVCMPGTSP : XX3Form_Rcr<60, 75,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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"xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare,
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[(set v4i32:$XT,
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(int_ppc_vsx_xvcmpgtsp v4f32:$XA, v4f32:$XB))]>;
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// Move Instructions
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// Move Instructions
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def XSABSDP : XX2Form<60, 345,
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def XSABSDP : XX2Form<60, 345,
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165
test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll
Normal file
165
test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll
Normal file
@ -0,0 +1,165 @@
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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@vda = common global <2 x double> zeroinitializer, align 16
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@vdb = common global <2 x double> zeroinitializer, align 16
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@vdr = common global <2 x double> zeroinitializer, align 16
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@vfa = common global <4 x float> zeroinitializer, align 16
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@vfb = common global <4 x float> zeroinitializer, align 16
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@vfr = common global <4 x float> zeroinitializer, align 16
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@vbllr = common global <2 x i64> zeroinitializer, align 16
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@vbir = common global <4 x i32> zeroinitializer, align 16
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@vblla = common global <2 x i64> zeroinitializer, align 16
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@vbllb = common global <2 x i64> zeroinitializer, align 16
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@vbia = common global <4 x i32> zeroinitializer, align 16
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@vbib = common global <4 x i32> zeroinitializer, align 16
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; Function Attrs: nounwind
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define void @test1() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @vdr, align 16
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ret void
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; CHECK-LABEL: @test1
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; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test2() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @vfr, align 16
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ret void
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; CHECK-LABEL: @test2
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; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test3() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vda, align 16
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%2 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %1)
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store <2 x double> %2, <2 x double>* @vdr, align 16
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ret void
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; CHECK-LABEL: @test3
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; CHECK: xvrdpip {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test4() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfa, align 16
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%2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %1)
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store <4 x float> %2, <4 x float>* @vfr, align 16
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ret void
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; CHECK-LABEL: @test4
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; CHECK: xvrspip {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test5() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test5
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; CHECK: xvcmpeqdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test6() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test6
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; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test7() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test7
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; CHECK: xvcmpgedp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test8() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test8
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; CHECK: xvcmpgesp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test9() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test9
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; CHECK: xvcmpgtdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test10() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test10
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; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
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