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Refactor ARM subarchitecture parsing
According to a FIXME in ARMMCTargetDesc.cpp the ARM version parsing should be in the Triple helper class. Patch by: Gabor Ballabas git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin
parent
50e72958aa
commit
7b4a688246
@ -78,6 +78,22 @@ public:
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spir, // SPIR: standard portable IR for OpenCL 32-bit version
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spir64 // SPIR: standard portable IR for OpenCL 64-bit version
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};
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enum SubArchType {
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NoSubArch,
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ARMSubArch_v8,
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ARMSubArch_v7,
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ARMSubArch_v7em,
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ARMSubArch_v7m,
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ARMSubArch_v7s,
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ARMSubArch_v6,
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ARMSubArch_v6m,
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ARMSubArch_v6t2,
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ARMSubArch_v5,
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ARMSubArch_v5te,
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ARMSubArch_v4t,
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ARMSubArch_v4
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};
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enum VendorType {
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UnknownVendor,
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@ -148,6 +164,9 @@ private:
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/// The parsed arch type.
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ArchType Arch;
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/// The parsed subarchitecture type.
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SubArchType SubArch;
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/// The parsed vendor type.
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VendorType Vendor;
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@ -190,6 +209,9 @@ public:
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/// getArch - Get the parsed architecture type of this triple.
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ArchType getArch() const { return Arch; }
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/// getSubArch - get the parsed subarchitecture type for this triple.
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SubArchType getSubArch() const { return SubArch; }
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/// getVendor - Get the parsed vendor type of this triple.
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VendorType getVendor() const { return Vendor; }
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@ -350,6 +350,26 @@ static Triple::ObjectFormatType parseFormat(StringRef EnvironmentName) {
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.Default(Triple::UnknownObjectFormat);
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}
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static Triple::SubArchType parseSubArch(StringRef SubArchName) {
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return StringSwitch<Triple::SubArchType>(SubArchName)
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.EndsWith("v8", Triple::ARMSubArch_v8)
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.EndsWith("v8a", Triple::ARMSubArch_v8)
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.EndsWith("v7", Triple::ARMSubArch_v7)
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.EndsWith("v7a", Triple::ARMSubArch_v7)
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.EndsWith("v7em", Triple::ARMSubArch_v7em)
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.EndsWith("v7m", Triple::ARMSubArch_v7m)
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.EndsWith("v7s", Triple::ARMSubArch_v7s)
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.EndsWith("v6", Triple::ARMSubArch_v6)
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.EndsWith("v6m", Triple::ARMSubArch_v6m)
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.EndsWith("v6t2", Triple::ARMSubArch_v6t2)
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.EndsWith("v5", Triple::ARMSubArch_v5)
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.EndsWith("v5t", Triple::ARMSubArch_v5)
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.EndsWith("v5te", Triple::ARMSubArch_v5te)
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.EndsWith("v4t", Triple::ARMSubArch_v4t)
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.EndsWith("v4", Triple::ARMSubArch_v4)
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.Default(Triple::NoSubArch);
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}
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static const char *getObjectFormatTypeName(Triple::ObjectFormatType Kind) {
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switch (Kind) {
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case Triple::UnknownObjectFormat: return "";
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@ -375,6 +395,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
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Triple::Triple(const Twine &Str)
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: Data(Str.str()),
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Arch(parseArch(getArchName())),
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SubArch(parseSubArch(getArchName())),
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Vendor(parseVendor(getVendorName())),
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OS(parseOS(getOSName())),
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Environment(parseEnvironment(getEnvironmentName())),
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@ -392,6 +413,7 @@ Triple::Triple(const Twine &Str)
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Triple::Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr)
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: Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr).str()),
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Arch(parseArch(ArchStr.str())),
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SubArch(parseSubArch(ArchStr.str())),
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Vendor(parseVendor(VendorStr.str())),
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OS(parseOS(OSStr.str())),
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Environment(), ObjectFormat(Triple::UnknownObjectFormat) {
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@ -408,6 +430,7 @@ Triple::Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr,
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: Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr + Twine('-') +
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EnvironmentStr).str()),
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Arch(parseArch(ArchStr.str())),
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SubArch(parseSubArch(ArchStr.str())),
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Vendor(parseVendor(VendorStr.str())),
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OS(parseOS(OSStr.str())),
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Environment(parseEnvironment(EnvironmentStr.str())),
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@ -84,93 +84,89 @@ static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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Triple triple(TT);
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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unsigned Len = TT.size();
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unsigned Idx = 0;
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// FIXME: Enhance Triple helper class to extract ARM version.
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bool isThumb = triple.getArch() == Triple::thumb ||
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triple.getArch() == Triple::thumbeb;
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if (Len >= 5 && TT.substr(0, 4) == "armv")
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Idx = 4;
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else if (Len >= 7 && TT.substr(0, 6) == "armebv")
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Idx = 6;
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else if (Len >= 7 && TT.substr(0, 6) == "thumbv")
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Idx = 6;
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else if (Len >= 9 && TT.substr(0, 8) == "thumbebv")
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Idx = 8;
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bool NoCPU = CPU == "generic" || CPU.empty();
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std::string ARMArchFeature;
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if (Idx) {
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unsigned SubVer = TT[Idx];
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if (SubVer == '8') {
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if (NoCPU)
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// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
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// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
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// FeatureT2XtPk, FeatureCrypto, FeatureCRC
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ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
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"+trustzone,+t2xtpk,+crypto,+crc";
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else
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// Use CPU to figure out the exact features
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ARMArchFeature = "+v8";
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} else if (SubVer == '7') {
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if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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isThumb = true;
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if (NoCPU)
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// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
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if (NoCPU)
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// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
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// FeatureT2XtPk, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else if (Len >= Idx+2 && TT[Idx+1] == 's') {
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if (NoCPU)
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// v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
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// Swift
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ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else {
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// v7 CPUs have lots of different feature sets. If no CPU is specified,
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// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
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// the "minimum" feature set and use CPU string to figure out the exact
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// features.
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if (NoCPU)
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// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
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ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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}
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} else if (SubVer == '6') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
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ARMArchFeature = "+v6t2";
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else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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isThumb = true;
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if (NoCPU)
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// v6m: FeatureNoARM, FeatureMClass
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ARMArchFeature = "+v6m,+noarm,+mclass";
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else
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ARMArchFeature = "+v6";
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} else
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ARMArchFeature = "+v6";
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} else if (SubVer == '5') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
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ARMArchFeature = "+v5te";
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else
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ARMArchFeature = "+v5t";
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} else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
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ARMArchFeature = "+v4t";
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switch (triple.getSubArch()) {
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case Triple::ARMSubArch_v8:
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if (NoCPU)
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// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
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// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
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// FeatureT2XtPk, FeatureCrypto, FeatureCRC
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ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
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"+trustzone,+t2xtpk,+crypto,+crc";
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else
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// Use CPU to figure out the exact features
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ARMArchFeature = "+v8";
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break;
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case Triple::ARMSubArch_v7m:
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isThumb = true;
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if (NoCPU)
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// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v7em:
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if (NoCPU)
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// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
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// FeatureT2XtPk, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v7s:
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if (NoCPU)
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// v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
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// Swift
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ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v7:
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// v7 CPUs have lots of different feature sets. If no CPU is specified,
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// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
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// the "minimum" feature set and use CPU string to figure out the exact
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// features.
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if (NoCPU)
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// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
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ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v6t2:
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ARMArchFeature = "+v6t2";
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break;
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case Triple::ARMSubArch_v6m:
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isThumb = true;
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if (NoCPU)
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// v6m: FeatureNoARM, FeatureMClass
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ARMArchFeature = "+v6m,+noarm,+mclass";
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else
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ARMArchFeature = "+v6";
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break;
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case Triple::ARMSubArch_v6:
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ARMArchFeature = "+v6";
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break;
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case Triple::ARMSubArch_v5te:
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ARMArchFeature = "+v5te";
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break;
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case Triple::ARMSubArch_v5:
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ARMArchFeature = "+v5t";
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break;
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case Triple::ARMSubArch_v4t:
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ARMArchFeature = "+v4t";
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break;
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case Triple::NoSubArch:
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case Triple::ARMSubArch_v4:
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ARMArchFeature = "+v4";
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break;
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}
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if (isThumb) {
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