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Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-08-11 07:17:46 +00:00
parent 8d62e713ea
commit 7b4d31176e
6 changed files with 15 additions and 13 deletions
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10
test/CodeGen/ARM/div.ll
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@@ -1,13 +1,9 @@
; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECK-ARM
; RUN: llc < %s -march=arm -mcpu=cortex-m3 \
; RUN: | FileCheck %s -check-prefix=CHECK-ARMV7M
define i32 @f1(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f1
; CHECK-ARM: __divsi3
; CHECK-ARMV7M: f1
; CHECK-ARMV7M: sdiv
%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@@ -16,8 +12,6 @@ define i32 @f2(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f2
; CHECK-ARM: __udivsi3
; CHECK-ARMV7M: f2
; CHECK-ARMV7M: udiv
%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@@ -26,8 +20,6 @@ define i32 @f3(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f3
; CHECK-ARM: __modsi3
; CHECK-ARMV7M: f3
; CHECK-ARMV7M: sdiv
%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@@ -36,8 +28,6 @@ define i32 @f4(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f4
; CHECK-ARM: __umodsi3
; CHECK-ARMV7M: f4
; CHECK-ARMV7M: udiv
%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}