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Change the arg lowering code to use copyfromreg from vregs associated

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with incoming arguments instead of the pregs themselves.  This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-09-13 19:33:40 +00:00
parent 8c4469840e
commit 7b738342f0
1 changed files with 17 additions and 12 deletions
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29
lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/Function.h" #include "llvm/Function.h"
using namespace llvm; using namespace llvm;
@@ -310,6 +311,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock& BB = MF.front(); MachineBasicBlock& BB = MF.front();
SSARegMap *RegMap = MF.getSSARegMap();
std::vector<SDOperand> ArgValues; std::vector<SDOperand> ArgValues;
unsigned ArgOffset = 24; unsigned ArgOffset = 24;
@@ -344,9 +346,9 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
ObjSize = 4; ObjSize = 4;
if (!ArgLive) break; if (!ArgLive) break;
if (GPR_remaining > 0) { if (GPR_remaining > 0) {
MF.addLiveIn(GPR[GPR_idx]); unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), MF.addLiveIn(GPR[GPR_idx], VReg);
GPR[GPR_idx], MVT::i32); argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
if (ObjectVT != MVT::i32) { if (ObjectVT != MVT::i32) {
unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
: ISD::AssertZext; : ISD::AssertZext;
@@ -362,15 +364,17 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
if (!ArgLive) break; if (!ArgLive) break;
if (GPR_remaining > 0) { if (GPR_remaining > 0) {
SDOperand argHi, argLo; SDOperand argHi, argLo;
MF.addLiveIn(GPR[GPR_idx]); unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32); MF.addLiveIn(GPR[GPR_idx], VReg);
argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
// If we have two or more remaining argument registers, then both halves // If we have two or more remaining argument registers, then both halves
// of the i64 can be sourced from there. Otherwise, the lower half will // of the i64 can be sourced from there. Otherwise, the lower half will
// have to come off the stack. This can happen when an i64 is preceded // have to come off the stack. This can happen when an i64 is preceded
// by 28 bytes of arguments. // by 28 bytes of arguments.
if (GPR_remaining > 1) { if (GPR_remaining > 1) {
MF.addLiveIn(GPR[GPR_idx+1]); unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32); MF.addLiveIn(GPR[GPR_idx+1], VReg);
argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
} else { } else {
int FI = MFI->CreateFixedObject(4, ArgOffset+4); int FI = MFI->CreateFixedObject(4, ArgOffset+4);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
@@ -389,9 +393,9 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
if (!ArgLive) break; if (!ArgLive) break;
if (FPR_remaining > 0) { if (FPR_remaining > 0) {
MF.addLiveIn(FPR[FPR_idx]); unsigned VReg = RegMap->createVirtualRegister(&PPC32::FPRCRegClass);
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), MF.addLiveIn(FPR[FPR_idx], VReg);
FPR[FPR_idx], ObjectVT); argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
--FPR_remaining; --FPR_remaining;
++FPR_idx; ++FPR_idx;
} else { } else {
@@ -438,8 +442,9 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// result of va_next. // result of va_next.
std::vector<SDOperand> MemOps; std::vector<SDOperand> MemOps;
for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
MF.addLiveIn(GPR[GPR_idx]); unsigned VReg = RegMap->createVirtualRegister(&PPC32::GPRCRegClass);
SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32); MF.addLiveIn(GPR[GPR_idx], VReg);
SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
Val, FIN, DAG.getSrcValue(NULL)); Val, FIN, DAG.getSrcValue(NULL));
MemOps.push_back(Store); MemOps.push_back(Store);