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Use MachineInstrBuilder in a few CodeGen passes.

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This automatically passes a context pointer to MI->addOperand().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-12-20 18:08:06 +00:00
parent ffc7d3b0ad
commit 7b79b9862c
5 changed files with 12 additions and 18 deletions
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6
lib/CodeGen/IfConversion.cpp
View File

@ -19,6 +19,7 @@
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/MCInstrItineraries.h"
@ -994,14 +995,13 @@ static void UpdatePredRedefs(MachineInstr *MI, SmallSet<unsigned,4> &Redefs,
Redefs.erase(*SubRegs); Redefs.erase(*SubRegs);
} }
} }
MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
for (unsigned i = 0, e = Defs.size(); i != e; ++i) { for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
unsigned Reg = Defs[i]; unsigned Reg = Defs[i];
if (!Redefs.insert(Reg)) { if (!Redefs.insert(Reg)) {
if (AddImpUse) if (AddImpUse)
// Treat predicated update as read + write. // Treat predicated update as read + write.
MI->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
true/*IsImp*/,false/*IsKill*/,
false/*IsDead*/,true/*IsUndef*/));
} else { } else {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
Redefs.insert(*SubRegs); Redefs.insert(*SubRegs);

3
lib/CodeGen/MachineSSAUpdater.cpp
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@ -315,8 +315,7 @@ public:
/// the specified predecessor block. /// the specified predecessor block.
static void AddPHIOperand(MachineInstr *PHI, unsigned Val, static void AddPHIOperand(MachineInstr *PHI, unsigned Val,
MachineBasicBlock *Pred) { MachineBasicBlock *Pred) {
PHI->addOperand(MachineOperand::CreateReg(Val, false)); MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred);
PHI->addOperand(MachineOperand::CreateMBB(Pred));
} }
/// InstrIsPHI - Check if an instruction is a PHI. /// InstrIsPHI - Check if an instruction is a PHI.

8
lib/CodeGen/PostRASchedulerList.cpp
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@ -30,6 +30,7 @@
#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h"
@ -464,13 +465,10 @@ bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
MO.setIsKill(false); MO.setIsKill(false);
bool AllDead = true; bool AllDead = true;
const unsigned SuperReg = MO.getReg(); const unsigned SuperReg = MO.getReg();
MachineInstrBuilder MIB(MF, MI);
for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) { for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
if (LiveRegs.test(*SubRegs)) { if (LiveRegs.test(*SubRegs)) {
MI->addOperand(MachineOperand::CreateReg(*SubRegs, MIB.addReg(*SubRegs, RegState::ImplicitDefine);
true /*IsDef*/,
true /*IsImp*/,
false /*IsKill*/,
false /*IsDead*/));
AllDead = false; AllDead = false;
} }
} }

6
lib/CodeGen/RegAllocFast.cpp
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@ -822,10 +822,8 @@ void RAFast::addRetOperands(MachineBasicBlock *MBB) {
} }
} }
if (!Found) if (!Found)
MI->addOperand(MachineOperand::CreateReg(Reg, MachineInstrBuilder(*MF, MI)
false /*IsDef*/, .addReg(Reg, llvm::RegState::Implicit | getKillRegState(hasDef));
true /*IsImp*/,
hasDef/*IsKill*/));
} }
} }

7
lib/CodeGen/TailDuplication.cpp
View File

@ -461,6 +461,7 @@ TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,
II != EE; ++II) { II != EE; ++II) {
if (!II->isPHI()) if (!II->isPHI())
break; break;
MachineInstrBuilder MIB(*FromBB->getParent(), II);
unsigned Idx = 0; unsigned Idx = 0;
for (unsigned i = 1, e = II->getNumOperands(); i != e; i += 2) { for (unsigned i = 1, e = II->getNumOperands(); i != e; i += 2) {
MachineOperand &MO = II->getOperand(i+1); MachineOperand &MO = II->getOperand(i+1);
@ -508,8 +509,7 @@ TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,
II->getOperand(Idx+1).setMBB(SrcBB); II->getOperand(Idx+1).setMBB(SrcBB);
Idx = 0; Idx = 0;
} else { } else {
II->addOperand(MachineOperand::CreateReg(SrcReg, false)); MIB.addReg(SrcReg).addMBB(SrcBB);
II->addOperand(MachineOperand::CreateMBB(SrcBB));
} }
} }
} else { } else {
@ -521,8 +521,7 @@ TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,
II->getOperand(Idx+1).setMBB(SrcBB); II->getOperand(Idx+1).setMBB(SrcBB);
Idx = 0; Idx = 0;
} else { } else {
II->addOperand(MachineOperand::CreateReg(Reg, false)); MIB.addReg(Reg).addMBB(SrcBB);
II->addOperand(MachineOperand::CreateMBB(SrcBB));
} }
} }
} }