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Unbreak ARMBaseRegisterInfo::copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -660,26 +660,27 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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} else if (DestRC == ARM::DPRRegisterClass) {
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} else if (DestRC == ARM::DPRRegisterClass) {
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const ARMBaseRegisterInfo* TRI = &getRegisterInfo();
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const ARMBaseRegisterInfo* TRI = &getRegisterInfo();
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// If we do not found an instruction defining the reg, this means the
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// register should be live-in for this BB. It's always to better to use
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// NEON reg-reg moves.
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unsigned Domain = ARMII::DomainNEON;
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// Find the Machine Instruction which defines SrcReg.
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// Find the Machine Instruction which defines SrcReg.
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MachineBasicBlock::iterator J = (I == MBB.begin() ? I : prior(I));
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if (!MBB.empty()) {
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while (J != MBB.begin()) {
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MachineBasicBlock::iterator J = (I == MBB.begin() ? I : prior(I));
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if (J->modifiesRegister(SrcReg, TRI))
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while (J != MBB.begin()) {
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break;
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if (J->modifiesRegister(SrcReg, TRI))
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--J;
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break;
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}
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--J;
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}
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unsigned Domain;
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if (J->modifiesRegister(SrcReg, TRI)) {
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if (J->modifiesRegister(SrcReg, TRI)) {
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Domain = J->getDesc().TSFlags & ARMII::DomainMask;
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Domain = J->getDesc().TSFlags & ARMII::DomainMask;
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// Instructions in general domain are subreg accesses.
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// Instructions in general domain are subreg accesses.
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// Map them to NEON reg-reg moves.
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// Map them to NEON reg-reg moves.
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if (Domain == ARMII::DomainGeneral)
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if (Domain == ARMII::DomainGeneral)
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Domain = ARMII::DomainNEON;
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Domain = ARMII::DomainNEON;
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}
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} else {
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// We reached the beginning of the BB and found no instruction defining
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// the reg. This means that register should be live-in for this BB.
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// It's always to better to use NEON reg-reg moves.
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Domain = ARMII::DomainNEON;
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}
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}
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if ((Domain & ARMII::DomainNEON) && getSubtarget().hasNEON()) {
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if ((Domain & ARMII::DomainNEON) && getSubtarget().hasNEON()) {
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29
test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll
Normal file
29
test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll
Normal file
@ -0,0 +1,29 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8
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define arm_apcscc void @get_initial_mb16x16_cost() nounwind {
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entry:
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br i1 undef, label %bb4, label %bb1
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bb1: ; preds = %entry
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br label %bb7
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bb4: ; preds = %entry
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br i1 undef, label %bb7.thread, label %bb5
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bb5: ; preds = %bb4
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br label %bb7
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bb7.thread: ; preds = %bb4
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br label %bb8
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bb7: ; preds = %bb5, %bb1
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br i1 undef, label %bb8, label %bb10
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bb8: ; preds = %bb7, %bb7.thread
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%0 = phi double [ 5.120000e+02, %bb7.thread ], [ undef, %bb7 ] ; <double> [#uses=1]
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%1 = fdiv double %0, undef ; <double> [#uses=0]
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unreachable
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bb10: ; preds = %bb7
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ret void
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}
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