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Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5914,6 +5914,12 @@ bool SelectionDAG::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
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/// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if
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/// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if
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/// it cannot be inferred.
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/// it cannot be inferred.
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unsigned SelectionDAG::InferPtrAlignment(SDValue Ptr) const {
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unsigned SelectionDAG::InferPtrAlignment(SDValue Ptr) const {
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// If this is a GlobalAddress + cst, return the alignment.
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GlobalValue *GV;
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int64_t GVOffset = 0;
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if (TLI.isGAPlusOffset(Ptr.getNode(), GV, GVOffset))
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return MinAlign(GV->getAlignment(), GVOffset);
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// If this is a direct reference to a stack slot, use information about the
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// If this is a direct reference to a stack slot, use information about the
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// stack slot's alignment.
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// stack slot's alignment.
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int FrameIdx = 1 << 31;
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int FrameIdx = 1 << 31;
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@ -8327,16 +8327,6 @@ bool X86TargetLowering::isGAPlusOffset(SDNode *N,
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return TargetLowering::isGAPlusOffset(N, GA, Offset);
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return TargetLowering::isGAPlusOffset(N, GA, Offset);
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}
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}
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static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
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const TargetLowering &TLI) {
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GlobalValue *GV;
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int64_t Offset = 0;
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if (TLI.isGAPlusOffset(Base, GV, Offset))
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return (GV->getAlignment() >= N && (Offset % N) == 0);
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// DAG combine handles the stack object case.
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return false;
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}
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static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
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static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
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EVT EltVT, LoadSDNode *&LDBase,
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EVT EltVT, LoadSDNode *&LDBase,
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unsigned &LastLoadedElt,
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unsigned &LastLoadedElt,
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@ -8399,7 +8389,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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if (LastLoadedElt == NumElems - 1) {
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if (LastLoadedElt == NumElems - 1) {
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if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
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if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
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return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
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return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
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LD->getSrcValue(), LD->getSrcValueOffset(),
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LD->getSrcValue(), LD->getSrcValueOffset(),
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LD->isVolatile());
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LD->isVolatile());
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@ -2,17 +2,17 @@
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; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
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; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
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; RUN: grep bisl %t1.s | count 7
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; RUN: grep bisl %t1.s | count 7
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; RUN: grep ila %t1.s | count 1
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; RUN: grep ila %t1.s | count 1
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; RUN: grep rotqby %t1.s | count 6
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; RUN: grep rotqby %t1.s | count 5
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; RUN: grep lqa %t1.s | count 1
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; RUN: grep lqa %t1.s | count 1
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; RUN: grep lqd %t1.s | count 12
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; RUN: grep lqd %t1.s | count 12
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; RUN: grep dispatch_tab %t1.s | count 5
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; RUN: grep dispatch_tab %t1.s | count 5
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; RUN: grep bisl %t2.s | count 7
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; RUN: grep bisl %t2.s | count 7
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; RUN: grep ilhu %t2.s | count 2
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; RUN: grep ilhu %t2.s | count 2
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; RUN: grep iohl %t2.s | count 2
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; RUN: grep iohl %t2.s | count 2
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; RUN: grep rotqby %t2.s | count 6
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; RUN: grep rotqby %t2.s | count 5
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; RUN: grep lqd %t2.s | count 13
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; RUN: grep lqd %t2.s | count 13
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; RUN: grep ilhu %t2.s | count 2
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; RUN: grep ilhu %t2.s | count 2
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; RUN: grep ai %t2.s | count 9
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; RUN: grep ai %t2.s | count 8
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; RUN: grep dispatch_tab %t2.s | count 6
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; RUN: grep dispatch_tab %t2.s | count 6
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; ModuleID = 'call_indirect.bc'
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; ModuleID = 'call_indirect.bc'
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