mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-06 14:57:41 +00:00
Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
d7ecff49d9
commit
7be5dfd1a1
@ -924,10 +924,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// FIXME: Do we need to handle scalar-to-vector here?
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setOperationAction(ISD::MUL, MVT::v4i32, Legal);
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// Can turn SHL into an integer multiply.
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setOperationAction(ISD::SHL, MVT::v4i32, Custom);
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setOperationAction(ISD::SHL, MVT::v16i8, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
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@ -955,18 +951,32 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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if (Subtarget->hasXMMInt()) {
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setOperationAction(ISD::SRL, MVT::v2i64, Custom);
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setOperationAction(ISD::SRL, MVT::v4i32, Custom);
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setOperationAction(ISD::SRL, MVT::v16i8, Custom);
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setOperationAction(ISD::SRL, MVT::v8i16, Custom);
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setOperationAction(ISD::SRL, MVT::v16i8, Custom);
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setOperationAction(ISD::SHL, MVT::v2i64, Custom);
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setOperationAction(ISD::SHL, MVT::v4i32, Custom);
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setOperationAction(ISD::SHL, MVT::v8i16, Custom);
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setOperationAction(ISD::SHL, MVT::v16i8, Custom);
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setOperationAction(ISD::SRA, MVT::v4i32, Custom);
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setOperationAction(ISD::SRA, MVT::v8i16, Custom);
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setOperationAction(ISD::SRA, MVT::v16i8, Custom);
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if (Subtarget->hasAVX2()) {
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setOperationAction(ISD::SRL, MVT::v2i64, Legal);
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setOperationAction(ISD::SRL, MVT::v4i32, Legal);
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setOperationAction(ISD::SHL, MVT::v2i64, Legal);
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setOperationAction(ISD::SHL, MVT::v4i32, Legal);
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setOperationAction(ISD::SRA, MVT::v4i32, Legal);
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} else {
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setOperationAction(ISD::SRL, MVT::v2i64, Custom);
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setOperationAction(ISD::SRL, MVT::v4i32, Custom);
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setOperationAction(ISD::SHL, MVT::v2i64, Custom);
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setOperationAction(ISD::SHL, MVT::v4i32, Custom);
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setOperationAction(ISD::SRA, MVT::v4i32, Custom);
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}
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}
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if (Subtarget->hasSSE42() || Subtarget->hasAVX())
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@ -1009,18 +1019,14 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
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setOperationAction(ISD::SRL, MVT::v4i64, Custom);
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setOperationAction(ISD::SRL, MVT::v8i32, Custom);
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setOperationAction(ISD::SRL, MVT::v16i16, Custom);
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setOperationAction(ISD::SRL, MVT::v32i8, Custom);
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setOperationAction(ISD::SHL, MVT::v4i64, Custom);
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setOperationAction(ISD::SHL, MVT::v8i32, Custom);
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setOperationAction(ISD::SHL, MVT::v16i16, Custom);
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setOperationAction(ISD::SHL, MVT::v32i8, Custom);
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setOperationAction(ISD::SRA, MVT::v8i32, Custom);
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setOperationAction(ISD::SRA, MVT::v16i16, Custom);
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setOperationAction(ISD::SRA, MVT::v32i8, Custom);
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setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
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setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
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@ -1053,6 +1059,14 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// Don't lower v32i8 because there is no 128-bit byte mul
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setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
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setOperationAction(ISD::SRL, MVT::v4i64, Legal);
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setOperationAction(ISD::SRL, MVT::v8i32, Legal);
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setOperationAction(ISD::SHL, MVT::v4i64, Legal);
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setOperationAction(ISD::SHL, MVT::v8i32, Legal);
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setOperationAction(ISD::SRA, MVT::v8i32, Legal);
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} else {
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setOperationAction(ISD::ADD, MVT::v4i64, Custom);
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setOperationAction(ISD::ADD, MVT::v8i32, Custom);
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@ -1068,6 +1082,14 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::MUL, MVT::v8i32, Custom);
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setOperationAction(ISD::MUL, MVT::v16i16, Custom);
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// Don't lower v32i8 because there is no 128-bit byte mul
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setOperationAction(ISD::SRL, MVT::v4i64, Custom);
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setOperationAction(ISD::SRL, MVT::v8i32, Custom);
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setOperationAction(ISD::SHL, MVT::v4i64, Custom);
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setOperationAction(ISD::SHL, MVT::v8i32, Custom);
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setOperationAction(ISD::SRA, MVT::v8i32, Custom);
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}
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// Custom lower several nodes for 256-bit types.
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@ -9510,6 +9532,14 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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// Fix vector shift instructions where the last operand is a non-immediate
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// i32 value.
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case Intrinsic::x86_avx2_pslli_w:
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case Intrinsic::x86_avx2_pslli_d:
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case Intrinsic::x86_avx2_pslli_q:
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case Intrinsic::x86_avx2_psrli_w:
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case Intrinsic::x86_avx2_psrli_d:
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case Intrinsic::x86_avx2_psrli_q:
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case Intrinsic::x86_avx2_psrai_w:
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case Intrinsic::x86_avx2_psrai_d:
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case Intrinsic::x86_sse2_pslli_w:
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case Intrinsic::x86_sse2_pslli_d:
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case Intrinsic::x86_sse2_pslli_q:
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@ -9557,6 +9587,30 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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case Intrinsic::x86_sse2_psrai_d:
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NewIntNo = Intrinsic::x86_sse2_psra_d;
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break;
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case Intrinsic::x86_avx2_pslli_w:
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NewIntNo = Intrinsic::x86_avx2_psll_w;
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break;
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case Intrinsic::x86_avx2_pslli_d:
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NewIntNo = Intrinsic::x86_avx2_psll_d;
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break;
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case Intrinsic::x86_avx2_pslli_q:
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NewIntNo = Intrinsic::x86_avx2_psll_q;
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break;
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case Intrinsic::x86_avx2_psrli_w:
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NewIntNo = Intrinsic::x86_avx2_psrl_w;
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break;
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case Intrinsic::x86_avx2_psrli_d:
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NewIntNo = Intrinsic::x86_avx2_psrl_d;
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break;
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case Intrinsic::x86_avx2_psrli_q:
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NewIntNo = Intrinsic::x86_avx2_psrl_q;
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break;
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case Intrinsic::x86_avx2_psrai_w:
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NewIntNo = Intrinsic::x86_avx2_psra_w;
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break;
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case Intrinsic::x86_avx2_psrai_d:
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NewIntNo = Intrinsic::x86_avx2_psra_d;
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break;
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default: {
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ShAmtVT = MVT::v2i32;
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switch (IntNo) {
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@ -10251,52 +10305,6 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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// AVX2 variable shifts
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if (Subtarget->hasAVX2()) {
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if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psllv_d, MVT::i32),
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R, Amt);
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if (VT == MVT::v8i32 && Op->getOpcode() == ISD::SHL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psllv_d_256, MVT::i32),
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R, Amt);
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if (VT == MVT::v2i64 && Op->getOpcode() == ISD::SHL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psllv_q, MVT::i32),
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R, Amt);
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if (VT == MVT::v4i64 && Op->getOpcode() == ISD::SHL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psllv_q_256, MVT::i32),
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R, Amt);
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if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SRL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrlv_d, MVT::i32),
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R, Amt);
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if (VT == MVT::v8i32 && Op->getOpcode() == ISD::SRL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrlv_d_256, MVT::i32),
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R, Amt);
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if (VT == MVT::v2i64 && Op->getOpcode() == ISD::SRL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrlv_q, MVT::i32),
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R, Amt);
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if (VT == MVT::v4i64 && Op->getOpcode() == ISD::SRL)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrlv_q_256, MVT::i32),
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R, Amt);
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if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SRA)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrav_d, MVT::i32),
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R, Amt);
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if (VT == MVT::v8i32 && Op->getOpcode() == ISD::SRA)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrav_d_256, MVT::i32),
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R, Amt);
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}
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// Lower SHL with variable shift amount.
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if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
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Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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@ -13464,7 +13472,9 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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if (!Subtarget->hasXMMInt())
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return SDValue();
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if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
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if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
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(!Subtarget->hasAVX2() ||
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(VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
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return SDValue();
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SDValue ShAmtOp = N->getOperand(1);
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@ -13537,6 +13547,18 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v4i64)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v8i32)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v16i16)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
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ValOp, BaseShAmt);
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break;
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case ISD::SRA:
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if (VT == MVT::v4i32)
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@ -13547,6 +13569,14 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v8i32)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v16i16)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
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ValOp, BaseShAmt);
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break;
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case ISD::SRL:
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if (VT == MVT::v2i64)
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@ -13561,6 +13591,18 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v4i64)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v8i32)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
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ValOp, BaseShAmt);
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if (VT == MVT::v16i16)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
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ValOp, BaseShAmt);
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break;
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}
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return SDValue();
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@ -7713,3 +7713,52 @@ defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", int_x86_avx2_psrlv_q,
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defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", int_x86_avx2_psrav_d,
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int_x86_avx2_psrav_d_256>;
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let Predicates = [HasAVX2] in {
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def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
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(VPSLLVDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
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(VPSLLVQrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (srl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
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(VPSRLVDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
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(VPSRLVQrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
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(VPSRAVDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
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(VPSLLVDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
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(VPSLLVQYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (srl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
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(VPSRLVDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
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(VPSRLVQYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
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(VPSRAVDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i32 (shl (v4i32 VR128:$src1),
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(v4i32 (bitconvert (memopv2i64 addr:$src2))))),
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(VPSLLVDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
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(VPSLLVQrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (srl (v4i32 VR128:$src1),
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(v4i32 (bitconvert (memopv2i64 addr:$src2))))),
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(VPSRLVDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
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(VPSRLVQrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (sra (v4i32 VR128:$src1),
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(v4i32 (bitconvert (memopv2i64 addr:$src2))))),
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(VPSRAVDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v8i32 (shl (v8i32 VR256:$src1),
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(v8i32 (bitconvert (memopv4i64 addr:$src2))))),
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(VPSLLVDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
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(VPSLLVQYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8i32 (srl (v8i32 VR256:$src1),
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(v8i32 (bitconvert (memopv4i64 addr:$src2))))),
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(VPSRLVDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
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(VPSRLVQYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i32 (sra (v8i32 VR256:$src1),
|
||||
(v8i32 (bitconvert (memopv4i64 addr:$src2))))),
|
||||
(VPSRAVDYrm VR256:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
@ -62,6 +62,45 @@ define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
|
||||
ret <16 x i16> %s
|
||||
}
|
||||
|
||||
; CHECK: vpsrlw
|
||||
; CHECK: pand
|
||||
; CHECK: pxor
|
||||
; CHECK: psubb
|
||||
; CHECK: vpsrlw
|
||||
; CHECK: pand
|
||||
; CHECK: pxor
|
||||
; CHECK: psubb
|
||||
define <32 x i8> @vshift09(<32 x i8> %a) nounwind readnone {
|
||||
%s = ashr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
|
||||
ret <32 x i8> %s
|
||||
}
|
||||
|
||||
; CHECK: pxor
|
||||
; CHECK: pcmpgtb
|
||||
; CHECK: pcmpgtb
|
||||
define <32 x i8> @vshift10(<32 x i8> %a) nounwind readnone {
|
||||
%s = ashr <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
|
||||
ret <32 x i8> %s
|
||||
}
|
||||
|
||||
; CHECK: vpsrlw
|
||||
; CHECK: pand
|
||||
; CHECK: vpsrlw
|
||||
; CHECK: pand
|
||||
define <32 x i8> @vshift11(<32 x i8> %a) nounwind readnone {
|
||||
%s = lshr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
|
||||
ret <32 x i8> %s
|
||||
}
|
||||
|
||||
; CHECK: vpsllw
|
||||
; CHECK: pand
|
||||
; CHECK: vpsllw
|
||||
; CHECK: pand
|
||||
define <32 x i8> @vshift12(<32 x i8> %a) nounwind readnone {
|
||||
%s = shl <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
|
||||
ret <32 x i8> %s
|
||||
}
|
||||
|
||||
;;; Support variable shifts
|
||||
; CHECK: _vshift08
|
||||
; CHECK: vextractf128 $1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user