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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-04 10:30:01 +00:00
Indentation fixes. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163682 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6924,9 +6924,9 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
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if (VT.getSizeInBits() == 8) {
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SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
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Op.getOperand(0), Op.getOperand(1));
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Op.getOperand(0), Op.getOperand(1));
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SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
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DAG.getValueType(VT));
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DAG.getValueType(VT));
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
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}
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@ -6941,9 +6941,9 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
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Op.getOperand(0)),
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Op.getOperand(1)));
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SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
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Op.getOperand(0), Op.getOperand(1));
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Op.getOperand(0), Op.getOperand(1));
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SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
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DAG.getValueType(VT));
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DAG.getValueType(VT));
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
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}
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@ -7027,9 +7027,9 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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// Transform it so it match pextrw which produces a 32-bit result.
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EVT EltVT = MVT::i32;
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SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
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Op.getOperand(0), Op.getOperand(1));
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Op.getOperand(0), Op.getOperand(1));
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SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
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DAG.getValueType(VT));
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DAG.getValueType(VT));
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
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}
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@ -7479,8 +7479,8 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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SDValue InFlag;
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DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
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SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
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DAG.getNode(X86ISD::GlobalBaseReg,
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DebugLoc(), PtrVT), InFlag);
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DAG.getNode(X86ISD::GlobalBaseReg,
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DebugLoc(), PtrVT), InFlag);
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InFlag = Chain.getValue(1);
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return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
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