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[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)

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Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.

Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise

On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.

Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.

The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').

Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().

Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4268


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-07-09 10:16:07 +00:00
parent 3b52084af8
commit 7c2ef822f7
13 changed files with 183 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files
test/CodeGen/Mips/eh-return32.ll
+9 -5
View File
@@ -1,4 +1,6 @@
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
declare void @llvm.eh.return.i32(i32, i8*)
declare void @foo(...)
@@ -9,7 +11,7 @@ entry:
call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
unreachable
; CHECK: f1
; CHECK: f1:
; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]]
; check that $a0-$a3 are saved on stack.
@@ -41,7 +43,8 @@ entry:
; CHECK: addiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2
; CHECK: jr $ra
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; CHECK: addu $sp, $sp, $3
}
@@ -50,7 +53,7 @@ entry:
call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
unreachable
; CHECK: f2
; CHECK: f2:
; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]]
; check that $a0-$a3 are saved on stack.
@@ -80,6 +83,7 @@ entry:
; CHECK: addiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2
; CHECK: jr $ra
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; CHECK: addu $sp, $sp, $3
}
test/CodeGen/Mips/eh-return64.ll
+10 -7
View File
@@ -1,5 +1,7 @@
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
declare void @llvm.eh.return.i64(i64, i8*)
declare void @foo(...)
@@ -10,7 +12,7 @@ entry:
call void @llvm.eh.return.i64(i64 %offset, i8* %handler)
unreachable
; CHECK: f1
; CHECK: f1:
; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]]
; check that $a0-$a3 are saved on stack.
@@ -42,9 +44,9 @@ entry:
; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2
; CHECK: jr $ra
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; CHECK: daddu $sp, $sp, $3
}
define void @f2(i64 %offset, i8* %handler) {
@@ -52,7 +54,7 @@ entry:
call void @llvm.eh.return.i64(i64 %offset, i8* %handler)
unreachable
; CHECK: f2
; CHECK: f2:
; CHECK: .cfi_startproc
; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]]
; CHECK: .cfi_def_cfa_offset [[spoffset]]
@@ -84,7 +86,8 @@ entry:
; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2
; CHECK: jr $ra
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; CHECK: daddu $sp, $sp, $3
; CHECK: .cfi_endproc
}
test/CodeGen/Mips/llvm-ir/ret.ll
+61 -22
View File
@@ -4,67 +4,94 @@
; test constant generation here.
;
; We'll test pointer returns in a separate file since the relocation model
; affects it.
; affects it and it's undesirable to repeat the non-pointer returns for each
; relocation model.
; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1
; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1
; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1
; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
define void @ret_void() {
; ALL-LABEL: ret_void:
; ALL: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret void
}
define i8 @ret_i8() {
; ALL-LABEL: ret_i8:
; ALL-DAG: jr $ra
; ALL-DAG: addiu $2, $zero, 3
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i8 3
}
define i16 @ret_i16_3() {
; ALL-LABEL: ret_i16_3:
; ALL-DAG: jr $ra
; ALL-DAG: addiu $2, $zero, 3
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i16 3
}
define i16 @ret_i16_256() {
; ALL-LABEL: ret_i16_256:
; ALL-DAG: jr $ra
; ALL-DAG: addiu $2, $zero, 256
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i16 256
}
define i16 @ret_i16_257() {
; ALL-LABEL: ret_i16_257:
; ALL-DAG: jr $ra
; ALL-DAG: addiu $2, $zero, 257
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i16 257
}
define i32 @ret_i32_257() {
; ALL-LABEL: ret_i32_257:
; ALL-DAG: jr $ra
; ALL-DAG: addiu $2, $zero, 257
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i32 257
}
define i32 @ret_i32_65536() {
; ALL-LABEL: ret_i32_65536:
; ALL-DAG: jr $ra
; ALL-DAG: lui $2, 1
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i32 65536
}
define i32 @ret_i32_65537() {
; ALL-LABEL: ret_i32_65537:
; ALL: lui $[[T0:[0-9]+]], 1
; ALL-DAG: jr $ra
; ALL-DAG: ori $2, $[[T0]], 1
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i32 65537
}
@@ -77,7 +104,9 @@ define i64 @ret_i64_65537() {
; GPR64-DAG: daddiu $2, $[[T0]], 1
; ALL-DAG: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i64 65537
}
@@ -91,7 +120,9 @@ define i64 @ret_i64_281479271677952() {
; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
; GPR64-DAG: dsll $2, $[[T1]], 32
; ALL-DAG: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i64 281479271677952
}
@@ -108,11 +139,12 @@ define i64 @ret_i64_281479271809026() {
; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17
; GPR64-DAG: daddiu $2, $[[T1]], 2
; ALL-DAG: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i64 281479271809026
}
; TODO: f32
define float @ret_float_0x0() {
; ALL-LABEL: ret_float_0x0:
@@ -122,7 +154,9 @@ define float @ret_float_0x0() {
; DMTC-DAG: dmtc1 $zero, $f0
; ALL-DAG: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret float 0x0000000000000000
}
@@ -133,7 +167,8 @@ define float @ret_float_0x3() {
; O32-DAG: lwc1 $f0, %lo($CPI
; N64-DAG: lwc1 $f0, %got_ofst($CPI
; ALL-DAG: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
; float constants are written as double constants
ret float 0x36b8000000000000
@@ -150,7 +185,9 @@ define double @ret_double_0x0() {
; DMTC-DAG: dmtc1 $zero, $f0
; ALL-DAG: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret double 0x0000000000000000
}
@@ -161,6 +198,8 @@ define double @ret_double_0x3() {
; O32-DAG: ldc1 $f0, %lo($CPI
; N64-DAG: ldc1 $f0, %got_ofst($CPI
; ALL-DAG: jr $ra
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret double 0x0000000000000003
}