mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Change the PassManager from a reference to a pointer.
The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -56,7 +56,7 @@ public:
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protected:
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TargetMachine *TM;
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PassManagerBase ±
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PassManagerBase *PM;
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PassConfigImpl *Impl; // Internal data structures
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bool Initialized; // Flagged after all passes are configured.
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@ -207,7 +207,7 @@ TargetPassConfig::~TargetPassConfig() {
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// Out of line constructor provides default values for pass options and
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// registers all common codegen passes.
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TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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: ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false),
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: ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),
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DisableVerify(false),
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EnableTailMerge(true) {
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@ -234,7 +234,7 @@ TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
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}
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TargetPassConfig::TargetPassConfig()
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: ImmutablePass(ID), PM(*(PassManagerBase*)0) {
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: ImmutablePass(ID), PM(0) {
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llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
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}
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@ -269,16 +269,16 @@ AnalysisID TargetPassConfig::addPass(char &ID) {
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Pass *P = Pass::createPass(FinalID);
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if (!P)
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llvm_unreachable("Pass ID not registered");
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PM.add(P);
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PM->add(P);
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return FinalID;
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}
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void TargetPassConfig::printAndVerify(const char *Banner) const {
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if (TM->shouldPrintMachineCode())
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PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
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PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
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if (VerifyMachineCode)
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PM.add(createMachineVerifierPass(Banner));
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PM->add(createMachineVerifierPass(Banner));
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}
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/// Add common target configurable passes that perform LLVM IR to IR transforms
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@ -288,46 +288,46 @@ void TargetPassConfig::addIRPasses() {
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// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
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// BasicAliasAnalysis wins if they disagree. This is intended to help
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// support "obvious" type-punning idioms.
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PM.add(createTypeBasedAliasAnalysisPass());
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PM.add(createBasicAliasAnalysisPass());
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PM->add(createTypeBasedAliasAnalysisPass());
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PM->add(createBasicAliasAnalysisPass());
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// Before running any passes, run the verifier to determine if the input
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// coming from the front-end and/or optimizer is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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PM->add(createVerifierPass());
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// Run loop strength reduction before anything else.
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if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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PM->add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
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PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
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}
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PM.add(createGCLoweringPass());
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PM->add(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM->add(createUnreachableBlockEliminationPass());
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}
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/// Add common passes that perform LLVM IR to IR transforms in preparation for
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/// instruction selection.
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void TargetPassConfig::addISelPrepare() {
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if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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PM->add(createCodeGenPreparePass(getTargetLowering()));
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PM.add(createStackProtectorPass(getTargetLowering()));
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PM->add(createStackProtectorPass(getTargetLowering()));
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addPreISel();
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if (PrintISelInput)
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PM.add(createPrintFunctionPass("\n\n"
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"*** Final LLVM Code input to ISel ***\n",
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&dbgs()));
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PM->add(createPrintFunctionPass("\n\n"
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"*** Final LLVM Code input to ISel ***\n",
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&dbgs()));
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// All passes which modify the LLVM IR are now complete; run the verifier
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// to ensure that the IR is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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PM->add(createVerifierPass());
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}
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/// Add the complete set of target-independent postISel code generator passes.
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@ -405,7 +405,7 @@ void TargetPassConfig::addMachinePasses() {
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// GC
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addPass(GCMachineCodeAnalysisID);
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if (PrintGCInfo)
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PM.add(createGCInfoPrinter(dbgs()));
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PM->add(createGCInfoPrinter(dbgs()));
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// Basic block placement.
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if (getOptLevel() != CodeGenOpt::None)
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@ -522,7 +522,7 @@ void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
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addPass(PHIEliminationID);
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addPass(TwoAddressInstructionPassID);
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PM.add(RegAllocPass);
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PM->add(RegAllocPass);
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printAndVerify("After Register Allocation");
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}
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@ -564,7 +564,7 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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printAndVerify("After Machine Scheduling");
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// Add the selected register allocation pass.
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PM.add(RegAllocPass);
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PM->add(RegAllocPass);
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printAndVerify("After Register Allocation");
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// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
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@ -136,22 +136,22 @@ TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
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bool ARMPassConfig::addPreISel() {
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if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
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PM.add(createGlobalMergePass(TM->getTargetLowering()));
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PM->add(createGlobalMergePass(TM->getTargetLowering()));
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return false;
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}
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bool ARMPassConfig::addInstSelector() {
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PM.add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
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PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
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return false;
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}
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bool ARMPassConfig::addPreRegAlloc() {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass(true));
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PM->add(createARMLoadStoreOptimizationPass(true));
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if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
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PM.add(createMLxExpansionPass());
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PM->add(createMLxExpansionPass());
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return true;
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}
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@ -159,23 +159,23 @@ bool ARMPassConfig::addPreSched2() {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (getOptLevel() != CodeGenOpt::None) {
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if (!getARMSubtarget().isThumb1Only()) {
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PM.add(createARMLoadStoreOptimizationPass());
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PM->add(createARMLoadStoreOptimizationPass());
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printAndVerify("After ARM load / store optimizer");
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}
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if (getARMSubtarget().hasNEON())
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PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
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PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
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}
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// Expand some pseudo instructions into multiple instructions to allow
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// proper scheduling.
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PM.add(createARMExpandPseudoPass());
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PM->add(createARMExpandPseudoPass());
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if (getOptLevel() != CodeGenOpt::None) {
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if (!getARMSubtarget().isThumb1Only())
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addPass(IfConverterID);
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}
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if (getARMSubtarget().isThumb2())
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PM.add(createThumb2ITBlockPass());
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PM->add(createThumb2ITBlockPass());
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return true;
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}
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@ -183,13 +183,13 @@ bool ARMPassConfig::addPreSched2() {
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bool ARMPassConfig::addPreEmitPass() {
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if (getARMSubtarget().isThumb2()) {
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if (!getARMSubtarget().prefers32BitThumb())
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PM.add(createThumb2SizeReductionPass());
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PM->add(createThumb2SizeReductionPass());
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// Constant island pass work on unbundled instructions.
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addPass(UnpackMachineBundlesID);
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}
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PM.add(createARMConstantIslandPass());
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PM->add(createARMConstantIslandPass());
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return true;
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}
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@ -72,7 +72,7 @@ TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
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bool SPUPassConfig::addInstSelector() {
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// Install an instruction selector.
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PM.add(createSPUISelDag(getSPUTargetMachine()));
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PM->add(createSPUISelDag(getSPUTargetMachine()));
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return false;
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}
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@ -85,9 +85,9 @@ bool SPUPassConfig::addPreEmitPass() {
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(BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
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"createTCESchedulerPass");
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if (schedulerCreator != NULL)
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PM.add(schedulerCreator("cellspu"));
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PM->add(schedulerCreator("cellspu"));
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//align instructions with nops/lnops for dual issue
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PM.add(createSPUNopFillerPass(getSPUTargetMachine()));
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PM->add(createSPUNopFillerPass(getSPUTargetMachine()));
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return true;
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}
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@ -100,23 +100,23 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
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}
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bool HexagonPassConfig::addInstSelector() {
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PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
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PM.add(createHexagonISelDag(getHexagonTargetMachine()));
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PM.add(createHexagonPeephole());
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PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
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PM->add(createHexagonISelDag(getHexagonTargetMachine()));
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PM->add(createHexagonPeephole());
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return false;
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}
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bool HexagonPassConfig::addPreRegAlloc() {
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if (!DisableHardwareLoops) {
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PM.add(createHexagonHardwareLoops());
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PM->add(createHexagonHardwareLoops());
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}
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return false;
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}
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bool HexagonPassConfig::addPostRegAlloc() {
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PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
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PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
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return true;
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}
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@ -129,14 +129,14 @@ bool HexagonPassConfig::addPreSched2() {
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bool HexagonPassConfig::addPreEmitPass() {
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if (!DisableHardwareLoops) {
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PM.add(createHexagonFixupHwLoops());
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PM->add(createHexagonFixupHwLoops());
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}
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// Expand Spill code for predicate registers.
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PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
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PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
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// Split up TFRcondsets into conditional transfers.
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PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
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PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
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return false;
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}
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@ -68,7 +68,7 @@ TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) {
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// Install an instruction selector pass using
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// the ISelDag to gen MBlaze code.
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bool MBlazePassConfig::addInstSelector() {
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PM.add(createMBlazeISelDag(getMBlazeTargetMachine()));
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PM->add(createMBlazeISelDag(getMBlazeTargetMachine()));
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return false;
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}
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@ -76,6 +76,6 @@ bool MBlazePassConfig::addInstSelector() {
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MBlazePassConfig::addPreEmitPass() {
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PM.add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
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PM->add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
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return true;
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}
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@ -60,12 +60,12 @@ TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
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bool MSP430PassConfig::addInstSelector() {
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// Install an instruction selector.
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PM.add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
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PM->add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
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return false;
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}
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bool MSP430PassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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PM.add(createMSP430BranchSelectionPass());
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PM->add(createMSP430BranchSelectionPass());
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return false;
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}
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@ -117,18 +117,16 @@ TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsPassConfig::addInstSelector()
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{
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PM.add(createMipsISelDag(getMipsTargetMachine()));
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bool MipsPassConfig::addInstSelector() {
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PM->add(createMipsISelDag(getMipsTargetMachine()));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MipsPassConfig::addPreEmitPass()
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{
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PM.add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
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bool MipsPassConfig::addPreEmitPass() {
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PM->add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
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return true;
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}
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@ -136,12 +134,12 @@ bool MipsPassConfig::addPreRegAlloc() {
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// Do not restore $gp if target is Mips64.
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// In N32/64, $gp is a callee-saved register.
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if (!getMipsSubtarget().hasMips64())
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PM.add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
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PM->add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
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return true;
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}
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bool MipsPassConfig::addPreSched2() {
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PM.add(createMipsExpandPseudoPass(getMipsTargetMachine()));
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PM->add(createMipsExpandPseudoPass(getMipsTargetMachine()));
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return true;
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}
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@ -130,7 +130,7 @@ TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) {
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}
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bool PTXPassConfig::addInstSelector() {
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PM.add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
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PM->add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
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return false;
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}
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@ -145,7 +145,7 @@ void PTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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bool PTXPassConfig::addPostRegAlloc() {
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// PTXMFInfoExtract must after register allocation!
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//PM.add(createPTXMFInfoExtract(getPTXTargetMachine()));
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//PM->add(createPTXMFInfoExtract(getPTXTargetMachine()));
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return false;
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}
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@ -159,7 +159,7 @@ void PTXPassConfig::addMachineLateOptimization() {
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}
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bool PTXPassConfig::addPreEmitPass() {
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PM.add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
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PM.add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
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PM->add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
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PM->add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
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return true;
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}
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@ -98,13 +98,13 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
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bool PPCPassConfig::addInstSelector() {
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// Install an instruction selector.
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PM.add(createPPCISelDag(getPPCTargetMachine()));
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PM->add(createPPCISelDag(getPPCTargetMachine()));
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return false;
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}
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bool PPCPassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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PM.add(createPPCBranchSelectionPass());
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PM->add(createPPCBranchSelectionPass());
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return false;
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}
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@ -59,7 +59,7 @@ TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
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}
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bool SparcPassConfig::addInstSelector() {
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PM.add(createSparcISelDag(getSparcTargetMachine()));
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PM->add(createSparcISelDag(getSparcTargetMachine()));
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return false;
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}
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@ -67,8 +67,8 @@ bool SparcPassConfig::addInstSelector() {
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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bool SparcPassConfig::addPreEmitPass(){
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PM.add(createSparcFPMoverPass(getSparcTargetMachine()));
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PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
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PM->add(createSparcFPMoverPass(getSparcTargetMachine()));
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PM->add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
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return true;
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}
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@ -145,34 +145,34 @@ TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
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bool X86PassConfig::addInstSelector() {
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// Install an instruction selector.
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PM.add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
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PM->add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
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// For 32-bit, prepend instructions to set the "global base reg" for PIC.
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if (!getX86Subtarget().is64Bit())
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PM.add(createGlobalBaseRegPass());
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PM->add(createGlobalBaseRegPass());
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return false;
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}
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bool X86PassConfig::addPreRegAlloc() {
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PM.add(createX86MaxStackAlignmentHeuristicPass());
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PM->add(createX86MaxStackAlignmentHeuristicPass());
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return false; // -print-machineinstr shouldn't print after this.
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}
|
||||
|
||||
bool X86PassConfig::addPostRegAlloc() {
|
||||
PM.add(createX86FloatingPointStackifierPass());
|
||||
PM->add(createX86FloatingPointStackifierPass());
|
||||
return true; // -print-machineinstr should print after this.
|
||||
}
|
||||
|
||||
bool X86PassConfig::addPreEmitPass() {
|
||||
bool ShouldPrint = false;
|
||||
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
|
||||
PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
|
||||
PM->add(createExecutionDependencyFixPass(&X86::VR128RegClass));
|
||||
ShouldPrint = true;
|
||||
}
|
||||
|
||||
if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
|
||||
PM.add(createX86IssueVZeroUpperPass());
|
||||
PM->add(createX86IssueVZeroUpperPass());
|
||||
ShouldPrint = true;
|
||||
}
|
||||
|
||||
|
@ -55,7 +55,7 @@ TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
|
||||
}
|
||||
|
||||
bool XCorePassConfig::addInstSelector() {
|
||||
PM.add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
|
||||
PM->add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
|
||||
return false;
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user