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Fix treatment of ARM unallocated hint instructions.

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The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)

Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.

Patch by Mihail Popa <Mihail.Popa@arm.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179707 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
2013-04-17 18:46:12 +00:00
parent 403569373f
commit 7c4cf030a8
4 changed files with 30 additions and 5 deletions
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11
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -308,6 +308,8 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
@ -4496,6 +4498,15 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
return S;
}
static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder)
{
unsigned Imm = fieldFromInstruction(Insn, 0, 3);
if (Imm > 4) return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Imm));
return MCDisassembler::Success;
}
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;