From 7c64fe651ad4581ac66b6407116144442a8a7f03 Mon Sep 17 00:00:00 2001
From: Devang Patel <dpatel@apple.com>
Date: Mon, 23 Jan 2012 18:31:58 +0000
Subject: [PATCH] Intel syntax: Parse segment registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/AsmParser/X86AsmParser.cpp | 20 ++++++++++++++++----
 test/MC/X86/intel-syntax.s                |  2 ++
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index a47e24a7c23..f2fee362611 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -54,7 +54,7 @@ private:
   X86Operand *ParseATTOperand();
   X86Operand *ParseIntelOperand();
   X86Operand *ParseIntelMemOperand();
-  X86Operand *ParseIntelBracExpression(unsigned Size);
+  X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
   X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
 
   bool ParseDirectiveWord(unsigned Size, SMLoc L);
@@ -593,8 +593,9 @@ static unsigned getIntelMemOperandSize(StringRef OpStr) {
   return Size;
 }
 
-X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
-  unsigned SegReg = 0, BaseReg = 0, IndexReg = 0, Scale = 1;
+X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
+                                                   unsigned Size) {
+  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
   SMLoc Start = Parser.getTok().getLoc(), End;
 
   const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
@@ -669,6 +670,7 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
 X86Operand *X86AsmParser::ParseIntelMemOperand() {
   const AsmToken &Tok = Parser.getTok();
   SMLoc Start = Parser.getTok().getLoc(), End;
+  unsigned SegReg = 0;
 
   unsigned Size = getIntelMemOperandSize(Tok.getString());
   if (Size) {
@@ -678,7 +680,17 @@ X86Operand *X86AsmParser::ParseIntelMemOperand() {
   }
 
   if (getLexer().is(AsmToken::LBrac))
-    return ParseIntelBracExpression(Size);
+    return ParseIntelBracExpression(SegReg, Size);
+
+  if (!ParseRegister(SegReg, Start, End)) {
+    // Handel SegReg : [ ... ]
+    if (getLexer().isNot(AsmToken::Colon))
+      return ErrorOperand(Start, "Expected ':' token!");
+    Parser.Lex(); // Eat :
+    if (getLexer().isNot(AsmToken::LBrac))
+      return ErrorOperand(Start, "Expected '[' token!");
+    return ParseIntelBracExpression(SegReg, Size);
+  }
 
   const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
   if (getParser().ParseExpression(Disp, End)) return 0;
diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s
index bf28173f734..fa58f1ee697 100644
--- a/test/MC/X86/intel-syntax.s
+++ b/test/MC/X86/intel-syntax.s
@@ -55,4 +55,6 @@ _main:
 	and	rax, -257
 // CHECK:	fld	%st(0)
 	fld	ST(0)
+// CHECK:	movl	%fs:(%rdi), %eax
+mov     EAX, DWORD PTR FS:[RDI]        
 	ret