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* Fix VRSHR and VSHR to have the correct encoding for the immediate.
* Update the NEON shift instruction test to expect what 'as' produces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
5881799d0c
commit
7c6b608a7c
@ -2288,17 +2288,17 @@ class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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// Shift by immediate,
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// both double- and quad-register.
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class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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Format f, InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType Ty, SDNode OpNode>
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Format f, InstrItinClass itin, Operand ImmTy,
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string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
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: N2VImm<op24, op23, op11_8, op7, 0, op4,
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(outs DPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), f, itin,
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(outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
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OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
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[(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
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class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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Format f, InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType Ty, SDNode OpNode>
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Format f, InstrItinClass itin, Operand ImmTy,
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string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
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: N2VImm<op24, op23, op11_8, op7, 1, op4,
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(outs QPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), f, itin,
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(outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
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OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
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[(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
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@ -3010,40 +3010,77 @@ multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
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// Neon 2-register vector shift by immediate,
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// with f of either N2RegVShLFrm or N2RegVShRFrm
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// element sizes of 8, 16, 32 and 64 bits:
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multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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SDNode OpNode, Format f> {
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multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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SDNode OpNode> {
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// 64-bit vector types.
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def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
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def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
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def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
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def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
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def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
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// imm6 = xxxxxx
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// 128-bit vector types.
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def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
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def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
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def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
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def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
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def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
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OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
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// imm6 = xxxxxx
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}
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multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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SDNode OpNode> {
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// 64-bit vector types.
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def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
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OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
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OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
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OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
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OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
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// imm6 = xxxxxx
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// 128-bit vector types.
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def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
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OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
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OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
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OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
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OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
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// imm6 = xxxxxx
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}
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@ -3920,14 +3957,13 @@ defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
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defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
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IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
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"vshl", "u", int_arm_neon_vshiftu>;
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// VSHL : Vector Shift Left (Immediate)
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defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
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N2RegVShLFrm>;
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defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
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// VSHR : Vector Shift Right (Immediate)
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defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
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N2RegVShRFrm>;
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defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
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N2RegVShRFrm>;
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defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
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defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
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// VSHLL : Vector Shift Left Long
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defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
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@ -3960,10 +3996,8 @@ defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
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IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
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"vrshl", "u", int_arm_neon_vrshiftu>;
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// VRSHR : Vector Rounding Shift Right
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defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
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N2RegVShRFrm>;
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defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
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N2RegVShRFrm>;
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defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
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defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
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// VRSHRN : Vector Rounding Shift Right and Narrow
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defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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@ -3977,13 +4011,11 @@ defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
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IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
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"vqshl", "u", int_arm_neon_vqshiftu>;
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// VQSHL : Vector Saturating Shift Left (Immediate)
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defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
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N2RegVShLFrm>;
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defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
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N2RegVShLFrm>;
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defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
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defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
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// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
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defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
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N2RegVShLFrm>;
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defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
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// VQSHRN : Vector Saturating Shift Right and Narrow
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defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
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@ -1,174 +1,173 @@
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
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@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3]
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_foo:
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@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3]
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vshl.u8 d16, d17, d16
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@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3]
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@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3]
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vshl.u16 d16, d17, d16
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@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3]
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@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3]
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vshl.u32 d16, d17, d16
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@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3]
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@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3]
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vshl.u64 d16, d17, d16
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@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2]
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@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2]
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vshl.i8 d16, d16, #7
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@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2]
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@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2]
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vshl.i16 d16, d16, #15
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@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2]
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@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2]
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vshl.i32 d16, d16, #31
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@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2]
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@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2]
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vshl.i64 d16, d16, #63
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@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3]
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@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3]
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vshl.u8 q8, q9, q8
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@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3]
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@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3]
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vshl.u16 q8, q9, q8
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@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3]
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@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3]
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vshl.u32 q8, q9, q8
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@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3]
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@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3]
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vshl.u64 q8, q9, q8
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@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2]
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@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2]
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vshl.i8 q8, q8, #7
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@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2]
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@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2]
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vshl.i16 q8, q8, #15
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@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2]
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@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2]
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vshl.i32 q8, q8, #31
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@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2]
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@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2]
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vshl.i64 q8, q8, #63
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@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3]
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vshr.u8 d16, d16, #8
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@ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf3]
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vshr.u16 d16, d16, #16
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@ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf3]
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vshr.u32 d16, d16, #32
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@ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf3]
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vshr.u64 d16, d16, #64
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@ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf3]
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vshr.u8 q8, q8, #8
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@ CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf3]
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vshr.u16 q8, q8, #16
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@ CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf3]
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vshr.u32 q8, q8, #32
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@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3]
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vshr.u64 q8, q8, #64
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@ CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf2]
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vshr.s8 d16, d16, #8
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@ CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf2]
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vshr.s16 d16, d16, #16
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@ CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf2]
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vshr.s32 d16, d16, #32
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@ CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf2]
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vshr.s64 d16, d16, #64
|
||||
@ CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf2]
|
||||
vshr.s8 q8, q8, #8
|
||||
@ CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf2]
|
||||
vshr.s16 q8, q8, #16
|
||||
@ CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf2
|
||||
vshr.s32 q8, q8, #32
|
||||
@ CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf2]
|
||||
vshr.s64 q8, q8, #64
|
||||
@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2]
|
||||
@ CHECK: vshr.u8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf3]
|
||||
vshr.u8 d16, d16, #7
|
||||
@ CHECK: vshr.u16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf3]
|
||||
vshr.u16 d16, d16, #15
|
||||
@ CHECK: vshr.u32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf3]
|
||||
vshr.u32 d16, d16, #31
|
||||
@ CHECK: vshr.u64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf3]
|
||||
vshr.u64 d16, d16, #63
|
||||
@ CHECK: vshr.u8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf3]
|
||||
vshr.u8 q8, q8, #7
|
||||
@ CHECK: vshr.u16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf3]
|
||||
vshr.u16 q8, q8, #15
|
||||
@ CHECK: vshr.u32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf3]
|
||||
vshr.u32 q8, q8, #31
|
||||
@ CHECK: vshr.u64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf3]
|
||||
vshr.u64 q8, q8, #63
|
||||
@ CHECK: vshr.s8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf2]
|
||||
vshr.s8 d16, d16, #7
|
||||
@ CHECK: vshr.s16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf2]
|
||||
vshr.s16 d16, d16, #15
|
||||
@ CHECK: vshr.s32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf2]
|
||||
vshr.s32 d16, d16, #31
|
||||
@ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2]
|
||||
vshr.s64 d16, d16, #63
|
||||
@ CHECK: vshr.s8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf2]
|
||||
vshr.s8 q8, q8, #7
|
||||
@ CHECK: vshr.s16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf2]
|
||||
vshr.s16 q8, q8, #15
|
||||
@ CHECK: vshr.s32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf2]
|
||||
vshr.s32 q8, q8, #31
|
||||
@ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2]
|
||||
vshr.s64 q8, q8, #63
|
||||
@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2]
|
||||
vshll.s8 q8, d16, #7
|
||||
@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2]
|
||||
@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2]
|
||||
vshll.s16 q8, d16, #15
|
||||
@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2]
|
||||
@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2]
|
||||
vshll.s32 q8, d16, #31
|
||||
@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3]
|
||||
@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3]
|
||||
vshll.u8 q8, d16, #7
|
||||
@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3]
|
||||
@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3]
|
||||
vshll.u16 q8, d16, #15
|
||||
@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3]
|
||||
@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3]
|
||||
vshll.u32 q8, d16, #31
|
||||
@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3]
|
||||
@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3]
|
||||
vshll.i8 q8, d16, #8
|
||||
@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3]
|
||||
@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3]
|
||||
vshll.i16 q8, d16, #16
|
||||
@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3]
|
||||
@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3]
|
||||
vshll.i32 q8, d16, #32
|
||||
@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
|
||||
@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
|
||||
vshrn.i16 d16, q8, #8
|
||||
@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
|
||||
@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
|
||||
vshrn.i32 d16, q8, #16
|
||||
@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
|
||||
@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
|
||||
vshrn.i64 d16, q8, #32
|
||||
@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2]
|
||||
@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2]
|
||||
vrshl.s8 d16, d17, d16
|
||||
@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2]
|
||||
@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2]
|
||||
vrshl.s16 d16, d17, d16
|
||||
@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2]
|
||||
@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2]
|
||||
vrshl.s32 d16, d17, d16
|
||||
@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0
|
||||
@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf2]
|
||||
vrshl.s64 d16, d17, d16
|
||||
@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3]
|
||||
@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3]
|
||||
vrshl.u8 d16, d17, d16
|
||||
@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3]
|
||||
@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3]
|
||||
vrshl.u16 d16, d17, d16
|
||||
@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3]
|
||||
@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3]
|
||||
vrshl.u32 d16, d17, d16
|
||||
@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3]
|
||||
@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3]
|
||||
vrshl.u64 d16, d17, d16
|
||||
@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2]
|
||||
@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2]
|
||||
vrshl.s8 q8, q9, q8
|
||||
@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2]
|
||||
@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2]
|
||||
vrshl.s16 q8, q9, q8
|
||||
@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2]
|
||||
@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2]
|
||||
vrshl.s32 q8, q9, q8
|
||||
@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2]
|
||||
@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2]
|
||||
vrshl.s64 q8, q9, q8
|
||||
@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3]
|
||||
@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3]
|
||||
vrshl.u8 q8, q9, q8
|
||||
@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3]
|
||||
@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3]
|
||||
vrshl.u16 q8, q9, q8
|
||||
@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3]
|
||||
@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3]
|
||||
vrshl.u32 q8, q9, q8
|
||||
@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3]
|
||||
@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3]
|
||||
vrshl.u64 q8, q9, q8
|
||||
@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2]
|
||||
@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2]
|
||||
vrshr.s8 d16, d16, #8
|
||||
@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2]
|
||||
@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2]
|
||||
vrshr.s16 d16, d16, #16
|
||||
@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2]
|
||||
@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2]
|
||||
vrshr.s32 d16, d16, #32
|
||||
@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2]
|
||||
@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2]
|
||||
vrshr.s64 d16, d16, #64
|
||||
@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3]
|
||||
@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3]
|
||||
vrshr.u8 d16, d16, #8
|
||||
@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3]
|
||||
@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3]
|
||||
vrshr.u16 d16, d16, #16
|
||||
@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3]
|
||||
@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3]
|
||||
vrshr.u32 d16, d16, #32
|
||||
@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3]
|
||||
@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3]
|
||||
vrshr.u64 d16, d16, #64
|
||||
@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2]
|
||||
@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2]
|
||||
vrshr.s8 q8, q8, #8
|
||||
@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2]
|
||||
@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2]
|
||||
vrshr.s16 q8, q8, #16
|
||||
@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2]
|
||||
@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2]
|
||||
vrshr.s32 q8, q8, #32
|
||||
@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2]
|
||||
@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2]
|
||||
vrshr.s64 q8, q8, #64
|
||||
@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3]
|
||||
@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3]
|
||||
vrshr.u8 q8, q8, #8
|
||||
@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3]
|
||||
@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3]
|
||||
vrshr.u16 q8, q8, #16
|
||||
@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3]
|
||||
@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3]
|
||||
vrshr.u32 q8, q8, #32
|
||||
@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3]
|
||||
@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3]
|
||||
vrshr.u64 q8, q8, #64
|
||||
@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2]
|
||||
@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2]
|
||||
vrshrn.i16 d16, q8, #8
|
||||
@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2]
|
||||
@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2]
|
||||
vrshrn.i32 d16, q8, #16
|
||||
@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
|
||||
@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
|
||||
vrshrn.i64 d16, q8, #32
|
||||
|
||||
@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
|
||||
vqrshrn.s16 d16, q8, #4
|
||||
@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
|
||||
vqrshrn.s32 d16, q8, #13
|
||||
@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
|
||||
vqrshrn.s64 d16, q8, #13
|
||||
|
||||
@ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3]
|
||||
vqrshrn.u16 d16, q8, #4
|
||||
@ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3]
|
||||
vqrshrn.u32 d16, q8, #13
|
||||
@ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3]
|
||||
vqrshrn.u64 d16, q8, #13
|
||||
@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
|
||||
vqrshrn.s16 d16, q8, #4
|
||||
@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
|
||||
vqrshrn.s32 d16, q8, #13
|
||||
@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
|
||||
vqrshrn.s64 d16, q8, #13
|
||||
@ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3]
|
||||
vqrshrn.u16 d16, q8, #4
|
||||
@ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3]
|
||||
vqrshrn.u32 d16, q8, #13
|
||||
@ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3]
|
||||
vqrshrn.u64 d16, q8, #13
|
||||
|
||||
Loading…
Reference in New Issue
Block a user