From 7c79de7c65cc28beff8f4535a32b7e704fbdd298 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Wed, 19 Jan 2005 06:30:36 +0000
Subject: [PATCH] Ensure that each these functions generates a sh[rl]d
 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19682 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/shift-double.llx | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 test/CodeGen/X86/shift-double.llx

diff --git a/test/CodeGen/X86/shift-double.llx b/test/CodeGen/X86/shift-double.llx
new file mode 100644
index 00000000000..ee3bc1e9925
--- /dev/null
+++ b/test/CodeGen/X86/shift-double.llx
@@ -0,0 +1,22 @@
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -disable-pattern-isel=0 | grep sh[lr]d | wc -l | grep 4
+
+long %test1(long %X, ubyte %C) {
+	%Y = shl long %X, ubyte %C
+	ret long %Y
+}
+long %test2(long %X, ubyte %C) {
+	%Y = shr long %X, ubyte %C
+	ret long %Y
+}
+ulong %test3(ulong %X, ubyte %C) {
+	%Y = shr ulong %X, ubyte %C
+	ret ulong %Y
+}
+
+uint %test4(uint %A, uint %B, ubyte %C) {
+	%X = shl uint %A, ubyte %C
+	%Cv = sub ubyte 32, %C
+	%Y = shr uint %B, ubyte %Cv
+	%Z = or uint %Y, %X
+	ret uint %Z
+}