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Rename SPARC V8 target to be the LLVM SPARC target.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-02-05 05:50:24 +00:00
parent 213845367c
commit 7c90f73a1b
18 changed files with 532 additions and 538 deletions
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37
lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -1,4 +1,4 @@
//===-- DelaySlotFiller.cpp - SparcV8 delay slot filler -------------------===//
//===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -11,17 +11,16 @@
//
//===----------------------------------------------------------------------===//
#include "SparcV8.h"
#include "Sparc.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/Statistic.h"
using namespace llvm;
namespace {
Statistic<> FilledSlots ("delayslotfiller", "Num. of delay slots filled");
Statistic<> FilledSlots("delayslotfiller", "Num. of delay slots filled");
struct Filler : public MachineFunctionPass {
/// Target machine description which we query for reg. names, data
@ -30,42 +29,42 @@ namespace {
TargetMachine &TM;
const TargetInstrInfo *TII;
Filler (TargetMachine &tm) : TM (tm), TII (tm.getInstrInfo ()) { }
Filler(TargetMachine &tm) : TM(tm), TII(tm.getInstrInfo()) { }
virtual const char *getPassName () const {
return "SparcV8 Delay Slot Filler";
virtual const char *getPassName() const {
return "SPARC Delay Slot Filler";
}
bool runOnMachineBasicBlock (MachineBasicBlock &MBB);
bool runOnMachineFunction (MachineFunction &F) {
bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction(MachineFunction &F) {
bool Changed = false;
for (MachineFunction::iterator FI = F.begin (), FE = F.end ();
for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI)
Changed |= runOnMachineBasicBlock (*FI);
Changed |= runOnMachineBasicBlock(*FI);
return Changed;
}
};
} // end of anonymous namespace
/// createSparcV8DelaySlotFillerPass - Returns a pass that fills in delay
/// slots in SparcV8 MachineFunctions
/// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
/// slots in Sparc MachineFunctions
///
FunctionPass *llvm::createSparcV8DelaySlotFillerPass (TargetMachine &tm) {
return new Filler (tm);
FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
return new Filler(tm);
}
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
/// Currently, we fill delay slots with NOPs. We assume there is only one
/// delay slot per delayed instruction.
///
bool Filler::runOnMachineBasicBlock (MachineBasicBlock &MBB) {
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I)
if (TII->hasDelaySlot (I->getOpcode ())) {
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
if (TII->hasDelaySlot(I->getOpcode())) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI (MBB, J, V8::NOP, 0);
BuildMI(MBB, J, SP::NOP, 0);
++FilledSlots;
Changed = true;
}

46
lib/Target/Sparc/FPMover.cpp
View File

@ -1,4 +1,4 @@
//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
//===-- FPMover.cpp - Sparc double-precision floating point move fixer ----===//
//
// The LLVM Compiler Infrastructure
//
@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
#include "SparcV8.h"
#include "SparcV8Subtarget.h"
#include "Sparc.h"
#include "SparcSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetMachine.h"
@ -34,7 +34,7 @@ namespace {
FPMover(TargetMachine &tm) : TM(tm) { }
virtual const char *getPassName() const {
return "SparcV8 Double-FP Move Fixer";
return "Sparc Double-FP Move Fixer";
}
bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
@ -42,10 +42,10 @@ namespace {
};
} // end of anonymous namespace
/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD
/// createSparcFPMoverPass - Returns a pass that turns FpMOVD
/// instructions into FMOVS instructions
///
FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) {
FunctionPass *llvm::createSparcFPMoverPass(TargetMachine &tm) {
return new FPMover(tm);
}
@ -54,16 +54,16 @@ FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) {
static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg,
unsigned &OddReg) {
static const unsigned EvenHalvesOfPairs[] = {
V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14,
V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30
SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14,
SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30
};
static const unsigned OddHalvesOfPairs[] = {
V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15,
V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31
SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15,
SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31
};
static const unsigned DoubleRegsInOrder[] = {
V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8,
V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15
SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8,
SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15
};
for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
if (DoubleRegsInOrder[i] == DoubleReg) {
@ -80,12 +80,12 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
MachineInstr *MI = I++;
if (MI->getOpcode() == V8::FpMOVD || MI->getOpcode() == V8::FpABSD ||
MI->getOpcode() == V8::FpNEGD) {
if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
MI->getOpcode() == SP::FpNEGD) {
Changed = true;
unsigned DestDReg = MI->getOperand(0).getReg();
unsigned SrcDReg = MI->getOperand(1).getReg();
if (DestDReg == SrcDReg && MI->getOpcode() == V8::FpMOVD) {
if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) {
MBB.erase(MI); // Eliminate the noop copy.
++NoopFpDs;
continue;
@ -95,12 +95,12 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
if (MI->getOpcode() == V8::FpMOVD)
MI->setOpcode(V8::FMOVS);
else if (MI->getOpcode() == V8::FpNEGD)
MI->setOpcode(V8::FNEGS);
else if (MI->getOpcode() == V8::FpABSD)
MI->setOpcode(V8::FABSS);
if (MI->getOpcode() == SP::FpMOVD)
MI->setOpcode(SP::FMOVS);
else if (MI->getOpcode() == SP::FpNEGD)
MI->setOpcode(SP::FNEGS);
else if (MI->getOpcode() == SP::FpABSD)
MI->setOpcode(SP::FABSS);
else
assert(0 && "Unknown opcode!");
@ -109,7 +109,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
}
++NumFpDs;
@ -121,7 +121,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool FPMover::runOnMachineFunction(MachineFunction &F) {
// If the target has V9 instructions, the fp-mover pseudos will never be
// emitted. Avoid a scan of the instructions to improve compile time.
if (TM.getSubtarget<SparcV8Subtarget>().isV9())
if (TM.getSubtarget<SparcSubtarget>().isV9())
return false;
bool Changed = false;

14
lib/Target/Sparc/Makefile
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@ -1,4 +1,4 @@
##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
@ -7,14 +7,14 @@
#
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = LLVMSparcV8
TARGET = SparcV8
LIBRARYNAME = LLVMSparc
TARGET = Sparc
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
SparcV8GenDAGISel.inc SparcV8GenSubtarget.inc
BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
SparcGenDAGISel.inc SparcGenSubtarget.inc
include $(LEVEL)/Makefile.common

89
lib/Target/Sparc/Sparc.h
View File

@ -1,4 +1,4 @@
//===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -8,43 +8,40 @@
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
// SparcV8 back-end.
// Sparc back-end.
//
//===----------------------------------------------------------------------===//
#ifndef TARGET_SPARCV8_H
#define TARGET_SPARCV8_H
#ifndef TARGET_SPARC_H
#define TARGET_SPARC_H
#include <iosfwd>
#include <cassert>
namespace llvm {
class FunctionPass;
class TargetMachine;
FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
TargetMachine &TM);
FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcV8FPMoverPass(TargetMachine &TM);
FunctionPass *createSparcISelDag(TargetMachine &TM);
FunctionPass *createSparcCodePrinterPass(std::ostream &OS, TargetMachine &TM);
FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
} // end namespace llvm;
// Defines symbolic names for SparcV8 registers. This defines a mapping from
// Defines symbolic names for Sparc registers. This defines a mapping from
// register name to register number.
//
#include "SparcV8GenRegisterNames.inc"
#include "SparcGenRegisterNames.inc"
// Defines symbolic names for the SparcV8 instructions.
// Defines symbolic names for the Sparc instructions.
//
#include "SparcV8GenInstrNames.inc"
#include "SparcGenInstrNames.inc"
namespace llvm {
// Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
// Enums corresponding to Sparc condition codes, both icc's and fcc's. These
// values must be kept in sync with the ones in the .td file.
namespace V8CC {
namespace SPCC {
enum CondCodes {
//ICC_A = 8 , // Always
//ICC_N = 0 , // Never
@ -82,37 +79,37 @@ namespace llvm {
};
}
static const char *SPARCCondCodeToString(V8CC::CondCodes CC) {
static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
switch (CC) {
default: assert(0 && "Unknown condition code");
case V8CC::ICC_NE: return "ne";
case V8CC::ICC_E: return "e";
case V8CC::ICC_G: return "g";
case V8CC::ICC_LE: return "le";
case V8CC::ICC_GE: return "ge";
case V8CC::ICC_L: return "l";
case V8CC::ICC_GU: return "gu";
case V8CC::ICC_LEU: return "leu";
case V8CC::ICC_CC: return "cc";
case V8CC::ICC_CS: return "cs";
case V8CC::ICC_POS: return "pos";
case V8CC::ICC_NEG: return "neg";
case V8CC::ICC_VC: return "vc";
case V8CC::ICC_VS: return "vs";
case V8CC::FCC_U: return "u";
case V8CC::FCC_G: return "g";
case V8CC::FCC_UG: return "ug";
case V8CC::FCC_L: return "l";
case V8CC::FCC_UL: return "ul";
case V8CC::FCC_LG: return "lg";
case V8CC::FCC_NE: return "ne";
case V8CC::FCC_E: return "e";
case V8CC::FCC_UE: return "ue";
case V8CC::FCC_GE: return "ge";
case V8CC::FCC_UGE: return "uge";
case V8CC::FCC_LE: return "le";
case V8CC::FCC_ULE: return "ule";
case V8CC::FCC_O: return "o";
case SPCC::ICC_NE: return "ne";
case SPCC::ICC_E: return "e";
case SPCC::ICC_G: return "g";
case SPCC::ICC_LE: return "le";
case SPCC::ICC_GE: return "ge";
case SPCC::ICC_L: return "l";
case SPCC::ICC_GU: return "gu";
case SPCC::ICC_LEU: return "leu";
case SPCC::ICC_CC: return "cc";
case SPCC::ICC_CS: return "cs";
case SPCC::ICC_POS: return "pos";
case SPCC::ICC_NEG: return "neg";
case SPCC::ICC_VC: return "vc";
case SPCC::ICC_VS: return "vs";
case SPCC::FCC_U: return "u";
case SPCC::FCC_G: return "g";
case SPCC::FCC_UG: return "ug";
case SPCC::FCC_L: return "l";
case SPCC::FCC_UL: return "ul";
case SPCC::FCC_LG: return "lg";
case SPCC::FCC_NE: return "ne";
case SPCC::FCC_E: return "e";
case SPCC::FCC_UE: return "ue";
case SPCC::FCC_GE: return "ge";
case SPCC::FCC_UGE: return "uge";
case SPCC::FCC_LE: return "le";
case SPCC::FCC_ULE: return "ule";
case SPCC::FCC_O: return "o";
}
}
} // end namespace llvm

12
lib/Target/Sparc/Sparc.td
View File

@ -1,4 +1,4 @@
//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
//===- Sparc.td - Describe the Sparc Target Machine -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -34,15 +34,15 @@ def FeatureVIS
// Register File Description
//===----------------------------------------------------------------------===//
include "SparcV8RegisterInfo.td"
include "SparcRegisterInfo.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "SparcV8InstrInfo.td"
include "SparcInstrInfo.td"
def SparcV8InstrInfo : InstrInfo {
def SparcInstrInfo : InstrInfo {
// Define how we want to layout our target-specific information field.
let TSFlagsFields = [];
let TSFlagsShifts = [];
@ -74,7 +74,7 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
def SparcV8 : Target {
def Sparc : Target {
// Pointers are 32-bits in size.
let PointerType = i32;
@ -82,5 +82,5 @@ def SparcV8 : Target {
let CalleeSavedRegisters = [];
// Pull in Instruction Info:
let InstructionSet = SparcV8InstrInfo;
let InstructionSet = SparcInstrInfo;
}

48
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -1,4 +1,4 @@
//===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -8,12 +8,12 @@
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
// of machine-dependent LLVM code to GAS-format Sparc V8 assembly language.
// of machine-dependent LLVM code to GAS-format SPARC assembly language.
//
//===----------------------------------------------------------------------===//
#include "SparcV8.h"
#include "SparcV8InstrInfo.h"
#include "Sparc.h"
#include "SparcInstrInfo.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
@ -35,8 +35,8 @@ using namespace llvm;
namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
struct SparcV8AsmPrinter : public AsmPrinter {
SparcV8AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
struct SparcAsmPrinter : public AsmPrinter {
SparcAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
Data16bitsDirective = "\t.half\t";
Data32bitsDirective = "\t.word\t";
Data64bitsDirective = 0; // .xword is only supported by V9.
@ -53,12 +53,12 @@ namespace {
ValueMapTy NumberForBB;
virtual const char *getPassName() const {
return "SparcV8 Assembly Printer";
return "Sparc Assembly Printer";
}
void printOperand(const MachineInstr *MI, int opNum);
void printMemOperand(const MachineInstr *MI, int opNum);
void printV8CCOperand(const MachineInstr *MI, int opNum);
void printCCOperand(const MachineInstr *MI, int opNum);
bool printInstruction(const MachineInstr *MI); // autogenerated.
bool runOnMachineFunction(MachineFunction &F);
@ -67,22 +67,22 @@ namespace {
};
} // end of anonymous namespace
#include "SparcV8GenAsmWriter.inc"
#include "SparcGenAsmWriter.inc"
/// createSparcV8CodePrinterPass - Returns a pass that prints the SparcV8
/// createSparcCodePrinterPass - Returns a pass that prints the SPARC
/// assembly code for a MachineFunction to the given output stream,
/// using the given target machine description. This should work
/// regardless of whether the function is in SSA form.
///
FunctionPass *llvm::createSparcV8CodePrinterPass (std::ostream &o,
TargetMachine &tm) {
return new SparcV8AsmPrinter(o, tm);
FunctionPass *llvm::createSparcCodePrinterPass(std::ostream &o,
TargetMachine &tm) {
return new SparcAsmPrinter(o, tm);
}
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
bool SparcV8AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
bool SparcAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
// Print out constants referenced by the function
@ -132,14 +132,14 @@ bool SparcV8AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
return false;
}
void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand (opNum);
const MRegisterInfo &RI = *TM.getRegisterInfo();
bool CloseParen = false;
if (MI->getOpcode() == V8::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
O << "%hi(";
CloseParen = true;
} else if ((MI->getOpcode() == V8::ORri || MI->getOpcode() == V8::ADDri)
} else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri)
&& !MO.isRegister() && !MO.isImmediate()) {
O << "%lo(";
CloseParen = true;
@ -170,7 +170,7 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
return;
}
case MachineOperand::MO_PCRelativeDisp:
std::cerr << "Shouldn't use addPCDisp() when building SparcV8 MachineInstrs";
std::cerr << "Shouldn't use addPCDisp() when building Sparc MachineInstrs";
abort ();
return;
case MachineOperand::MO_GlobalAddress:
@ -189,13 +189,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
if (CloseParen) O << ")";
}
void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
printOperand(MI, opNum);
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
if ((OpTy == MachineOperand::MO_VirtualRegister ||
OpTy == MachineOperand::MO_MachineRegister) &&
MI->getOperand(opNum+1).getReg() == V8::G0)
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
OpTy == MachineOperand::MO_UnextendedImmed) &&
@ -213,19 +213,19 @@ void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
}
}
void SparcV8AsmPrinter::printV8CCOperand(const MachineInstr *MI, int opNum) {
void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
int CC = (int)MI->getOperand(opNum).getImmedValue();
O << SPARCCondCodeToString((V8CC::CondCodes)CC);
O << SPARCCondCodeToString((SPCC::CondCodes)CC);
}
bool SparcV8AsmPrinter::doInitialization(Module &M) {
bool SparcAsmPrinter::doInitialization(Module &M) {
Mang = new Mangler(M);
return false; // success
}
bool SparcV8AsmPrinter::doFinalization(Module &M) {
bool SparcAsmPrinter::doFinalization(Module &M) {
const TargetData &TD = TM.getTargetData();
// Print out module-level global variables here.

350
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -1,4 +1,4 @@
//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,12 +7,12 @@
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the V8 target
// This file defines an instruction selector for the SPARC target.
//
//===----------------------------------------------------------------------===//
#include "SparcV8.h"
#include "SparcV8TargetMachine.h"
#include "Sparc.h"
#include "SparcTargetMachine.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@ -30,9 +30,9 @@ using namespace llvm;
// TargetLowering Implementation
//===----------------------------------------------------------------------===//
namespace V8ISD {
namespace SPISD {
enum {
FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
CMPICC, // Compare two GPR operands, set icc.
CMPFCC, // Compare two FP operands, set fcc.
BRICC, // Branch to dest on icc condition
@ -45,56 +45,56 @@ namespace V8ISD {
FTOI, // FP to Int within a FP register.
ITOF, // Int to FP within a FP register.
CALL, // A V8 call instruction.
CALL, // A call instruction.
RET_FLAG, // Return with a flag operand.
};
}
/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
/// condition.
static V8CC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown integer condition code!");
case ISD::SETEQ: return V8CC::ICC_E;
case ISD::SETNE: return V8CC::ICC_NE;
case ISD::SETLT: return V8CC::ICC_L;
case ISD::SETGT: return V8CC::ICC_G;
case ISD::SETLE: return V8CC::ICC_LE;
case ISD::SETGE: return V8CC::ICC_GE;
case ISD::SETULT: return V8CC::ICC_CS;
case ISD::SETULE: return V8CC::ICC_LEU;
case ISD::SETUGT: return V8CC::ICC_GU;
case ISD::SETUGE: return V8CC::ICC_CC;
case ISD::SETEQ: return SPCC::ICC_E;
case ISD::SETNE: return SPCC::ICC_NE;
case ISD::SETLT: return SPCC::ICC_L;
case ISD::SETGT: return SPCC::ICC_G;
case ISD::SETLE: return SPCC::ICC_LE;
case ISD::SETGE: return SPCC::ICC_GE;
case ISD::SETULT: return SPCC::ICC_CS;
case ISD::SETULE: return SPCC::ICC_LEU;
case ISD::SETUGT: return SPCC::ICC_GU;
case ISD::SETUGE: return SPCC::ICC_CC;
}
}
/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
/// FCC condition.
static V8CC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown fp condition code!");
case ISD::SETEQ: return V8CC::FCC_E;
case ISD::SETNE: return V8CC::FCC_NE;
case ISD::SETLT: return V8CC::FCC_L;
case ISD::SETGT: return V8CC::FCC_G;
case ISD::SETLE: return V8CC::FCC_LE;
case ISD::SETGE: return V8CC::FCC_GE;
case ISD::SETULT: return V8CC::FCC_UL;
case ISD::SETULE: return V8CC::FCC_ULE;
case ISD::SETUGT: return V8CC::FCC_UG;
case ISD::SETUGE: return V8CC::FCC_UGE;
case ISD::SETUO: return V8CC::FCC_U;
case ISD::SETO: return V8CC::FCC_O;
case ISD::SETONE: return V8CC::FCC_LG;
case ISD::SETUEQ: return V8CC::FCC_UE;
case ISD::SETEQ: return SPCC::FCC_E;
case ISD::SETNE: return SPCC::FCC_NE;
case ISD::SETLT: return SPCC::FCC_L;
case ISD::SETGT: return SPCC::FCC_G;
case ISD::SETLE: return SPCC::FCC_LE;
case ISD::SETGE: return SPCC::FCC_GE;
case ISD::SETULT: return SPCC::FCC_UL;
case ISD::SETULE: return SPCC::FCC_ULE;
case ISD::SETUGT: return SPCC::FCC_UG;
case ISD::SETUGE: return SPCC::FCC_UGE;
case ISD::SETUO: return SPCC::FCC_U;
case ISD::SETO: return SPCC::FCC_O;
case ISD::SETONE: return SPCC::FCC_LG;
case ISD::SETUEQ: return SPCC::FCC_UE;
}
}
namespace {
class SparcV8TargetLowering : public TargetLowering {
class SparcTargetLowering : public TargetLowering {
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
SparcV8TargetLowering(TargetMachine &TM);
SparcTargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
@ -120,13 +120,13 @@ namespace {
};
}
SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
// Set up the register classes.
addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
@ -175,7 +175,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// V8 has no intrinsics for these particular operations.
// SPARC has no intrinsics for these particular operations.
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
@ -218,42 +218,42 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
setStackPointerRegisterToSaveRestore(V8::O6);
setStackPointerRegisterToSaveRestore(SP::O6);
if (TM.getSubtarget<SparcV8Subtarget>().isV9()) {
if (TM.getSubtarget<SparcSubtarget>().isV9()) {
setOperationAction(ISD::CTPOP, MVT::i32, Legal);
}
computeRegisterProperties();
}
const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;
case V8ISD::CMPICC: return "V8ISD::CMPICC";
case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
case V8ISD::BRICC: return "V8ISD::BRICC";
case V8ISD::BRFCC: return "V8ISD::BRFCC";
case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
case V8ISD::Hi: return "V8ISD::Hi";
case V8ISD::Lo: return "V8ISD::Lo";
case V8ISD::FTOI: return "V8ISD::FTOI";
case V8ISD::ITOF: return "V8ISD::ITOF";
case V8ISD::CALL: return "V8ISD::CALL";
case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG";
case SPISD::CMPICC: return "SPISD::CMPICC";
case SPISD::CMPFCC: return "SPISD::CMPFCC";
case SPISD::BRICC: return "SPISD::BRICC";
case SPISD::BRFCC: return "SPISD::BRFCC";
case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
case SPISD::Hi: return "SPISD::Hi";
case SPISD::Lo: return "SPISD::Lo";
case SPISD::FTOI: return "SPISD::FTOI";
case SPISD::ITOF: return "SPISD::ITOF";
case SPISD::CALL: return "SPISD::CALL";
case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
}
}
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
bool SparcV8TargetLowering::
bool SparcTargetLowering::
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
switch (Op.getOpcode()) {
default: return false;
case V8ISD::SELECT_ICC:
case V8ISD::SELECT_FCC:
case SPISD::SELECT_ICC:
case SPISD::SELECT_FCC:
assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
// These operations are masked zero if both the left and the right are zero.
return MaskedValueIsZero(Op.getOperand(0), Mask) &&
@ -266,13 +266,13 @@ isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
/// either one or two GPRs, including FP values. TODO: we should pass FP values
/// in FP registers for fastcc functions.
std::vector<SDOperand>
SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
SSARegMap *RegMap = MF.getSSARegMap();
std::vector<SDOperand> ArgValues;
static const unsigned ArgRegs[] = {
V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
};
const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
@ -294,7 +294,7 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
if (CurArgReg < ArgRegEnd) ++CurArgReg;
ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
MF.addLiveIn(*CurArgReg++, VReg);
SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
if (ObjectVT != MVT::i32) {
@ -334,7 +334,7 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
// FP value is passed in an integer register.
unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
MF.addLiveIn(*CurArgReg++, VReg);
SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
@ -369,7 +369,7 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
} else {
SDOperand HiVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
MF.addLiveIn(*CurArgReg++, VRegHi);
HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
} else {
@ -380,7 +380,7 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
SDOperand LoVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
MF.addLiveIn(*CurArgReg++, VRegLo);
LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
} else {
@ -410,7 +410,7 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
VarArgsFrameOffset = ArgOffset;
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
MF.addLiveIn(*CurArgReg, VReg);
SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
@ -434,17 +434,17 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
case MVT::i8:
case MVT::i16:
case MVT::i32:
MF.addLiveOut(V8::I0);
MF.addLiveOut(SP::I0);
break;
case MVT::i64:
MF.addLiveOut(V8::I0);
MF.addLiveOut(V8::I1);
MF.addLiveOut(SP::I0);
MF.addLiveOut(SP::I1);
break;
case MVT::f32:
MF.addLiveOut(V8::F0);
MF.addLiveOut(SP::F0);
break;
case MVT::f64:
MF.addLiveOut(V8::D0);
MF.addLiveOut(SP::D0);
break;
}
@ -452,10 +452,10 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
}
std::pair<SDOperand, SDOperand>
SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
bool isVarArg, unsigned CC,
bool isTailCall, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG) {
SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
bool isVarArg, unsigned CC,
bool isTailCall, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
// Count the size of the outgoing arguments.
unsigned ArgsSize = 0;
@ -565,7 +565,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if (ValToStore.Val) {
if (!StackPtr.Val) {
StackPtr = DAG.getRegister(V8::O6, MVT::i32);
StackPtr = DAG.getRegister(SP::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
@ -581,7 +581,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
static const unsigned ArgRegs[] = {
V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
};
// Build a sequence of copy-to-reg nodes chained together with token chain
@ -605,7 +605,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Ops.push_back(Callee);
if (InFlag.Val)
Ops.push_back(InFlag);
Chain = DAG.getNode(V8ISD::CALL, NodeTys, Ops);
Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
InFlag = Chain.getValue(1);
MVT::ValueType RetTyVT = getValueType(RetTy);
@ -616,7 +616,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
case MVT::i1:
case MVT::i8:
case MVT::i16:
RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
Chain = RetVal.getValue(1);
// Add a note to keep track of whether it is sign or zero extended.
@ -625,20 +625,20 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
break;
case MVT::i32:
RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
Chain = RetVal.getValue(1);
break;
case MVT::f32:
RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
Chain = RetVal.getValue(1);
break;
case MVT::f64:
RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
break;
case MVT::i64:
SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
Lo.getValue(2));
RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
Chain = Hi.getValue(1);
@ -652,64 +652,64 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
return std::make_pair(RetVal, Chain);
}
std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
std::pair<SDOperand, SDOperand> SparcTargetLowering::
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG) {
assert(0 && "Unimp");
abort();
}
// Look at LHS/RHS/CC and see if they are a lowered V8 setcc instruction. If so
// set LHS/RHS and V8CC to the LHS/RHS of the setcc and V8CC to the condition.
// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
ISD::CondCode CC, unsigned &V8CC) {
ISD::CondCode CC, unsigned &SPCC) {
if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
CC == ISD::SETNE &&
((LHS.getOpcode() == V8ISD::SELECT_ICC &&
LHS.getOperand(3).getOpcode() == V8ISD::CMPICC) ||
(LHS.getOpcode() == V8ISD::SELECT_FCC &&
LHS.getOperand(3).getOpcode() == V8ISD::CMPFCC)) &&
((LHS.getOpcode() == SPISD::SELECT_ICC &&
LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
(LHS.getOpcode() == SPISD::SELECT_FCC &&
LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
isa<ConstantSDNode>(LHS.getOperand(0)) &&
isa<ConstantSDNode>(LHS.getOperand(1)) &&
cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
SDOperand CMPCC = LHS.getOperand(3);
V8CC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
LHS = CMPCC.getOperand(0);
RHS = CMPCC.getOperand(1);
}
}
SDOperand SparcV8TargetLowering::
SDOperand SparcTargetLowering::
LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
case ISD::ConstantPool: {
Constant *C = cast<ConstantPoolSDNode>(Op)->get();
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
cast<ConstantPoolSDNode>(Op)->getAlignment());
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
case ISD::FP_TO_SINT:
// Convert the fp value to integer in an FP register.
assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
case ISD::SINT_TO_FP: {
assert(Op.getOperand(0).getValueType() == MVT::i32);
SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
}
case ISD::BR_CC: {
SDOperand Chain = Op.getOperand(0);
@ -717,11 +717,11 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand LHS = Op.getOperand(2);
SDOperand RHS = Op.getOperand(3);
SDOperand Dest = Op.getOperand(4);
unsigned Opc, V8CC = ~0U;
unsigned Opc, SPCC = ~0U;
// If this is a br_cc of a "setcc", and if the setcc got lowered into
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
LookThroughSetCC(LHS, RHS, CC, V8CC);
LookThroughSetCC(LHS, RHS, CC, SPCC);
// Get the condition flag.
SDOperand CompareFlag;
@ -732,16 +732,16 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
if (V8CC == ~0U) V8CC = IntCondCCodeToICC(CC);
Opc = V8ISD::BRICC;
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = SPISD::BRICC;
} else {
CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
if (V8CC == ~0U) V8CC = FPCondCCodeToFCC(CC);
Opc = V8ISD::BRFCC;
CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
Opc = SPISD::BRFCC;
}
return DAG.getNode(Opc, MVT::Other, Chain, Dest,
DAG.getConstant(V8CC, MVT::i32), CompareFlag);
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
case ISD::SELECT_CC: {
SDOperand LHS = Op.getOperand(0);
@ -749,11 +749,11 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDOperand TrueVal = Op.getOperand(2);
SDOperand FalseVal = Op.getOperand(3);
unsigned Opc, V8CC = ~0U;
unsigned Opc, SPCC = ~0U;
// If this is a select_cc of a "setcc", and if the setcc got lowered into
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
LookThroughSetCC(LHS, RHS, CC, V8CC);
LookThroughSetCC(LHS, RHS, CC, SPCC);
SDOperand CompareFlag;
if (LHS.getValueType() == MVT::i32) {
@ -763,22 +763,22 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
Opc = V8ISD::SELECT_ICC;
if (V8CC == ~0U) V8CC = IntCondCCodeToICC(CC);
CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
Opc = SPISD::SELECT_ICC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
} else {
CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
Opc = V8ISD::SELECT_FCC;
if (V8CC == ~0U) V8CC = FPCondCCodeToFCC(CC);
CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
Opc = SPISD::SELECT_FCC;
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
}
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(V8CC, MVT::i32), CompareFlag);
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
DAG.getRegister(V8::I6, MVT::i32),
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(VarArgsFrameOffset, MVT::i32));
return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
Op.getOperand(1), Op.getOperand(2));
@ -827,46 +827,46 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
unsigned ArgReg;
switch(Op.getOperand(1).getValueType()) {
default: assert(0 && "Unknown type to return!");
case MVT::i32: ArgReg = V8::I0; break;
case MVT::f32: ArgReg = V8::F0; break;
case MVT::f64: ArgReg = V8::D0; break;
case MVT::i32: ArgReg = SP::I0; break;
case MVT::f32: ArgReg = SP::F0; break;
case MVT::f64: ArgReg = SP::D0; break;
}
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
SDOperand());
break;
}
case 3:
Copy = DAG.getCopyToReg(Op.getOperand(0), V8::I0, Op.getOperand(2),
Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
SDOperand());
Copy = DAG.getCopyToReg(Copy, V8::I1, Op.getOperand(1), Copy.getValue(1));
Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
break;
}
return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
}
}
MachineBasicBlock *
SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
unsigned BROpcode;
unsigned CC;
// Figure out the conditional branch opcode to use for this select_cc.
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SELECT_CC!");
case V8::SELECT_CC_Int_ICC:
case V8::SELECT_CC_FP_ICC:
case V8::SELECT_CC_DFP_ICC:
BROpcode = V8::BCOND;
case SP::SELECT_CC_Int_ICC:
case SP::SELECT_CC_FP_ICC:
case SP::SELECT_CC_DFP_ICC:
BROpcode = SP::BCOND;
break;
case V8::SELECT_CC_Int_FCC:
case V8::SELECT_CC_FP_FCC:
case V8::SELECT_CC_DFP_FCC:
BROpcode = V8::FBCOND;
case SP::SELECT_CC_Int_FCC:
case SP::SELECT_CC_FP_FCC:
case SP::SELECT_CC_DFP_FCC:
BROpcode = SP::FBCOND;
break;
}
CC = (V8CC::CondCodes)MI->getOperand(3).getImmedValue();
CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
// control-flow pattern. The incoming instruction knows the destination vreg
@ -904,7 +904,7 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
@ -917,20 +917,20 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
//===----------------------------------------------------------------------===//
//===--------------------------------------------------------------------===//
/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
/// instructions for SelectionDAG operations.
///
namespace {
class SparcV8DAGToDAGISel : public SelectionDAGISel {
SparcV8TargetLowering V8Lowering;
class SparcDAGToDAGISel : public SelectionDAGISel {
SparcTargetLowering Lowering;
/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
/// make the right decision when generating code for different targets.
const SparcV8Subtarget &Subtarget;
const SparcSubtarget &Subtarget;
public:
SparcV8DAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(V8Lowering), V8Lowering(TM),
Subtarget(TM.getSubtarget<SparcV8Subtarget>()) {
SparcDAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(Lowering), Lowering(TM),
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
}
SDOperand Select(SDOperand Op);
@ -944,17 +944,17 @@ public:
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
virtual const char *getPassName() const {
return "SparcV8 DAG->DAG Pattern Instruction Selection";
return "SPARC DAG->DAG Pattern Instruction Selection";
}
// Include the pieces autogenerated from the target description.
#include "SparcV8GenDAGISel.inc"
#include "SparcGenDAGISel.inc"
};
} // end anonymous namespace
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
DEBUG(BB->dump());
// Select target instructions for the DAG.
@ -966,7 +966,7 @@ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
ScheduleAndEmitDAG(DAG);
}
bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
SDOperand &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@ -988,12 +988,12 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
return true;
}
}
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
Base = Select(Addr.getOperand(1));
Offset = Addr.getOperand(0).getOperand(0);
return true;
}
if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
Base = Select(Addr.getOperand(0));
Offset = Addr.getOperand(1).getOperand(0);
return true;
@ -1004,15 +1004,15 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
return true;
}
bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
SDOperand &R2) {
bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
SDOperand &R2) {
if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::ADD) {
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
Addr.getOperand(1).getOpcode() == V8ISD::Lo)
if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
Addr.getOperand(1).getOpcode() == SPISD::Lo)
return false; // Let the reg+imm pattern catch this!
R1 = Select(Addr.getOperand(0));
R2 = Select(Addr.getOperand(1));
@ -1020,14 +1020,14 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
}
R1 = Select(Addr);
R2 = CurDAG->getRegister(V8::G0, MVT::i32);
R2 = CurDAG->getRegister(SP::G0, MVT::i32);
return true;
}
SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
SDOperand SparcDAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
N->getOpcode() < V8ISD::FIRST_NUMBER)
N->getOpcode() < SPISD::FIRST_NUMBER)
return Op; // Already selected.
// If this has already been converted, use it.
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
@ -1038,11 +1038,11 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
return CurDAG->SelectNodeTo(N, SP::ADDri, MVT::i32,
CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32));
return CodeGenMap[Op] =
CurDAG->getTargetNode(V8::ADDri, MVT::i32,
CurDAG->getTargetNode(SP::ADDri, MVT::i32,
CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32));
}
@ -1052,9 +1052,9 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
SDOperand RHSL = Select(N->getOperand(2));
SDOperand RHSH = Select(N->getOperand(3));
// FIXME, handle immediate RHS.
SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
SDOperand Low = CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
LHSL, RHSL);
SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
SDOperand Hi = CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH,
Low.getValue(1));
CodeGenMap[SDOperand(N, 0)] = Low;
CodeGenMap[SDOperand(N, 1)] = Hi;
@ -1066,9 +1066,9 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
SDOperand RHSL = Select(N->getOperand(2));
SDOperand RHSH = Select(N->getOperand(3));
// FIXME, handle immediate RHS.
SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
SDOperand Low = CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
LHSL, RHSL);
SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
SDOperand Hi = CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH,
Low.getValue(1));
CodeGenMap[SDOperand(N, 0)] = Low;
CodeGenMap[SDOperand(N, 1)] = Hi;
@ -1083,16 +1083,16 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
// Set the Y register to the high-part.
SDOperand TopPart;
if (N->getOpcode() == ISD::SDIV) {
TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
TopPart = CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
CurDAG->getTargetConstant(31, MVT::i32));
} else {
TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
}
TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
CurDAG->getRegister(V8::G0, MVT::i32));
TopPart = CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
CurDAG->getRegister(SP::G0, MVT::i32));
// FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
}
case ISD::MULHU:
@ -1100,13 +1100,13 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
// FIXME: Handle mul by immediate.
SDOperand MulLHS = Select(N->getOperand(0));
SDOperand MulRHS = Select(N->getOperand(1));
unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, Mul.getValue(1));
}
case V8ISD::CALL:
case SPISD::CALL:
// FIXME: This is a workaround for a bug in tblgen.
{ // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
// Emits: (CALL:void (tglobaladdr:i32):$dst)
@ -1121,10 +1121,10 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
SDOperand Result;
if (N->getNumOperands() == 3) {
InFlag = Select(N->getOperand(2));
Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
Chain, InFlag);
} else {
Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
Chain);
}
Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
@ -1139,9 +1139,9 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
}
/// createSparcV8ISelDag - This pass converts a legalized DAG into a
/// createSparcISelDag - This pass converts a legalized DAG into a
/// SPARC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
return new SparcV8DAGToDAGISel(TM);
FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
return new SparcDAGToDAGISel(TM);
}

16
lib/Target/Sparc/SparcInstrFormats.td
View File

@ -1,4 +1,4 @@
//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
//===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,10 +7,10 @@
//
//===----------------------------------------------------------------------===//
class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
class InstSP<dag ops, string asmstr, list<dag> pattern> : Instruction {
field bits<32> Inst;
let Namespace = "V8";
let Namespace = "SP";
bits<2> op;
let Inst{31-30} = op; // Top two bits are the 'op' field
@ -21,12 +21,12 @@ class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
}
//===----------------------------------------------------------------------===//
// Format #2 instruction classes in the SparcV8
// Format #2 instruction classes in the Sparc
//===----------------------------------------------------------------------===//
// Format 2 instructions
class F2<dag ops, string asmstr, list<dag> pattern>
: InstV8<ops, asmstr, pattern> {
: InstSP<ops, asmstr, pattern> {
bits<3> op2;
bits<22> imm22;
let op = 0; // op = 0
@ -58,11 +58,11 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
}
//===----------------------------------------------------------------------===//
// Format #3 instruction classes in the SparcV8
// Format #3 instruction classes in the Sparc
//===----------------------------------------------------------------------===//
class F3<dag ops, string asmstr, list<dag> pattern>
: InstV8<ops, asmstr, pattern> {
: InstSP<ops, asmstr, pattern> {
bits<5> rd;
bits<6> op3;
bits<5> rs1;
@ -76,7 +76,7 @@ class F3<dag ops, string asmstr, list<dag> pattern>
//
class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
bits<8> asi = 0; // asi not currently used in SparcV8
bits<8> asi = 0; // asi not currently used
bits<5> rs2;
let op = opVal;

50
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -1,4 +1,4 @@
//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,18 +7,18 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
// This file contains the Sparc implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#include "SparcV8InstrInfo.h"
#include "SparcV8.h"
#include "SparcInstrInfo.h"
#include "Sparc.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "SparcV8GenInstrInfo.inc"
#include "SparcGenInstrInfo.inc"
using namespace llvm;
SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST)
: TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])),
SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
: TargetInstrInfo(SparcInsts, sizeof(SparcInsts)/sizeof(SparcInsts[0])),
RI(ST) {
}
@ -29,29 +29,29 @@ static bool isZeroImm(const MachineOperand &op) {
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
// We look for 3 kinds of patterns here:
// or with G0 or 0
// add with G0 or 0
// fmovs or FpMOVD (pseudo double move).
if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
if (MI.getOperand(1).getReg() == V8::G0) {
if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
if (MI.getOperand(1).getReg() == SP::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (MI.getOperand(2).getReg() == V8::G0) {
} else if (MI.getOperand(2).getReg() == SP::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
} else if ((MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) &&
} else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
} else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD ||
MI.getOpcode() == V8::FMOVD) {
} else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
MI.getOpcode() == SP::FMOVD) {
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
@ -64,11 +64,11 @@ bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned SparcV8InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == V8::LDri ||
MI->getOpcode() == V8::LDFri ||
MI->getOpcode() == V8::LDDFri) {
unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == SP::LDri ||
MI->getOpcode() == SP::LDFri ||
MI->getOpcode() == SP::LDDFri) {
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
@ -83,11 +83,11 @@ unsigned SparcV8InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned SparcV8InstrInfo::isStoreToStackSlot(MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == V8::STri ||
MI->getOpcode() == V8::STFri ||
MI->getOpcode() == V8::STDFri) {
unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == SP::STri ||
MI->getOpcode() == SP::STFri ||
MI->getOpcode() == SP::STDFri) {
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(1).getImmedValue() == 0) {
FrameIndex = MI->getOperand(0).getFrameIndex();

20
lib/Target/Sparc/SparcInstrInfo.h
View File

@ -1,4 +1,4 @@
//===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,22 +7,22 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
// This file contains the Sparc implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef SPARCV8INSTRUCTIONINFO_H
#define SPARCV8INSTRUCTIONINFO_H
#ifndef SPARCINSTRUCTIONINFO_H
#define SPARCINSTRUCTIONINFO_H
#include "llvm/Target/TargetInstrInfo.h"
#include "SparcV8RegisterInfo.h"
#include "SparcRegisterInfo.h"
namespace llvm {
/// V8II - This namespace holds all of the target specific flags that
/// SPII - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
namespace V8II {
namespace SPII {
enum {
Pseudo = (1<<0),
Load = (1<<1),
@ -31,10 +31,10 @@ namespace V8II {
};
};
class SparcV8InstrInfo : public TargetInstrInfo {
const SparcV8RegisterInfo RI;
class SparcInstrInfo : public TargetInstrInfo {
const SparcRegisterInfo RI;
public:
SparcV8InstrInfo(SparcV8Subtarget &ST);
SparcInstrInfo(SparcSubtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should

148
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -1,4 +1,4 @@
//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file describes the SparcV8 instructions in TableGen format.
// This file describes the Sparc instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
@ -15,7 +15,7 @@
// Instruction format superclass
//===----------------------------------------------------------------------===//
include "SparcV8InstrFormats.td"
include "SparcInstrFormats.td"
//===----------------------------------------------------------------------===//
// Feature predicates.
@ -87,54 +87,54 @@ def brtarget : Operand<OtherVT>;
def calltarget : Operand<i32>;
// Operand for printing out a condition code.
let PrintMethod = "printV8CCOperand" in
def V8CC : Operand<i32>;
let PrintMethod = "printCCOperand" in
def CCOp : Operand<i32>;
def SDTV8cmpfcc :
def SDTSPcmpfcc :
SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
def SDTV8brcc :
def SDTSPbrcc :
SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
SDTCisVT<2, FlagVT>]>;
def SDTV8selectcc :
def SDTSPselectcc :
SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
def SDTV8FTOI :
def SDTSPFTOI :
SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
def SDTV8ITOF :
def SDTSPITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain]>;
def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain]>;
def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc>;
def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc>;
// These are target-independent nodes, but have target-specific formats.
def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, [SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, [SDNPHasChain]>;
def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def call : SDNode<"V8ISD::CALL", SDT_V8Call,
def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def call : SDNode<"SPISD::CALL", SDT_SPCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
//===----------------------------------------------------------------------===//
// SPARC Flag Conditions
//===----------------------------------------------------------------------===//
// Note that these values must be kept in sync with the V8CC::CondCode enum
// Note that these values must be kept in sync with the CCOp::CondCode enum
// values.
class ICC_VAL<int N> : PatLeaf<(i32 N)>;
def ICC_NE : ICC_VAL< 9>; // Not Equal
@ -175,7 +175,7 @@ def FCC_O : FCC_VAL<29>; // Ordered
// Pseudo instructions.
class Pseudo<dag ops, string asmstr, list<dag> pattern>
: InstV8<ops, asmstr, pattern>;
: InstSP<ops, asmstr, pattern>;
def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
@ -193,7 +193,7 @@ def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
let Predicates = [HasNoV9] in { // Only emit these in SP mode.
def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpMOVD $src, $dst", []>;
def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
@ -212,32 +212,32 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
def SELECT_CC_Int_ICC
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_ICC PSEUDO!",
[(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
[(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
imm:$Cond, ICC))]>;
def SELECT_CC_Int_FCC
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_FCC PSEUDO!",
[(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
[(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
imm:$Cond, FCC))]>;
def SELECT_CC_FP_ICC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_ICC PSEUDO!",
[(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
[(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
imm:$Cond, ICC))]>;
def SELECT_CC_FP_FCC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_FCC PSEUDO!",
[(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
[(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
imm:$Cond, FCC))]>;
def SELECT_CC_DFP_ICC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_ICC PSEUDO!",
[(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
[(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
imm:$Cond, ICC))]>;
def SELECT_CC_DFP_FCC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_FCC PSEUDO!",
[(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
[(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
imm:$Cond, FCC))]>;
}
@ -477,11 +477,11 @@ def SUBXri : F3_2<2, 0b001100,
def SUBCCrr : F3_1<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subcc $b, $c, $dst",
[(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
[(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>;
def SUBCCri : F3_2<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"subcc $b, $c, $dst",
[(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
[(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>;
def SUBXCCrr: F3_1<2, 0b011100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subxcc $b, $c, $dst", []>;
@ -533,7 +533,7 @@ def RESTOREri : F3_2<2, 0b111101,
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
// conditional branch class:
class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
: F2_2<cc, 0b010, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
@ -542,20 +542,20 @@ class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
}
let isBarrier = 1 in
def BA : BranchV8<0b1000, (ops brtarget:$dst),
def BA : BranchSP<0b1000, (ops brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
// FIXME: the encoding for the JIT should look at the condition field.
def BCOND : BranchV8<0, (ops brtarget:$dst, V8CC:$cc),
def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
"b$cc $dst",
[(V8bricc bb:$dst, imm:$cc, ICC)]>;
[(SPbricc bb:$dst, imm:$cc, ICC)]>;
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
// floating-point conditional branch class:
class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
: F2_2<cc, 0b110, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
@ -564,9 +564,9 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
}
// FIXME: the encoding for the JIT should look at the condition field.
def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
"fb$cc $dst",
[(V8brfcc bb:$dst, imm:$cc, FCC)]>;
[(SPbrfcc bb:$dst, imm:$cc, FCC)]>;
// Section B.24 - Call and Link Instruction, p. 125
@ -575,7 +575,7 @@ let Uses = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1, noResults = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
def CALL : InstV8<(ops calltarget:$dst),
def CALL : InstSP<(ops calltarget:$dst),
"call $dst", []> {
bits<30> disp;
let op = 1;
@ -610,21 +610,21 @@ def WRYri : F3_2<2, 0b110000,
def FITOS : F3_3<2, 0b110100, 0b011000100,
(ops FPRegs:$dst, FPRegs:$src),
"fitos $src, $dst",
[(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
[(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
def FITOD : F3_3<2, 0b110100, 0b011001000,
(ops DFPRegs:$dst, FPRegs:$src),
"fitod $src, $dst",
[(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
[(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3<2, 0b110100, 0b011010001,
(ops FPRegs:$dst, FPRegs:$src),
"fstoi $src, $dst",
[(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
[(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
def FDTOI : F3_3<2, 0b110100, 0b011010010,
(ops FPRegs:$dst, DFPRegs:$src),
"fdtoi $src, $dst",
[(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
[(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3<2, 0b110100, 0b011001001,
@ -711,11 +711,11 @@ def FDIVD : F3_3<2, 0b110100, 0b001001110,
def FCMPS : F3_3<2, 0b110101, 0b001010001,
(ops FPRegs:$src1, FPRegs:$src2),
"fcmps $src1, $src2\n\tnop",
[(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
[(set FCC, (SPcmpfcc FPRegs:$src1, FPRegs:$src2))]>;
def FCMPD : F3_3<2, 0b110101, 0b001010010,
(ops DFPRegs:$src1, DFPRegs:$src2),
"fcmpd $src1, $src2\n\tnop",
[(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
[(set FCC, (SPcmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
//===----------------------------------------------------------------------===//
@ -727,47 +727,47 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
// FIXME: Add instruction encodings for the JIT some day.
def MOVICCrr
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
"mov$cc %icc, $F, $dst",
[(set IntRegs:$dst,
(V8selecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
(SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
def MOVICCri
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
"mov$cc %icc, $F, $dst",
[(set IntRegs:$dst,
(V8selecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
(SPselecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
def MOVFCCrr
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
"mov$cc %fcc0, $F, $dst",
[(set IntRegs:$dst,
(V8selectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
(SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
def MOVFCCri
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
"mov$cc %fcc0, $F, $dst",
[(set IntRegs:$dst,
(V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
(SPselectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
def FMOVS_ICC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
"fmovs$cc %icc, $F, $dst",
[(set FPRegs:$dst,
(V8selecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
(SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
def FMOVD_ICC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
"fmovd$cc %icc, $F, $dst",
[(set DFPRegs:$dst,
(V8selecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
(SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
def FMOVS_FCC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
"fmovs$cc %fcc0, $F, $dst",
[(set FPRegs:$dst,
(V8selectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
(SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
def FMOVD_FCC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
"fmovd$cc %fcc0, $F, $dst",
[(set DFPRegs:$dst,
(V8selectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
(SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
}
@ -806,15 +806,15 @@ def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
// Global addresses, constant pool entries
def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
// Add reg, lo. This is used when taking the addr of a global/constpool entry.
def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
(ADDri IntRegs:$r, tglobaladdr:$in)>;
def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
(ADDri IntRegs:$r, tconstpool:$in)>;

132
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -1,4 +1,4 @@
//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,13 +7,13 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
// This file contains the SPARC implementation of the MRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "SparcV8.h"
#include "SparcV8RegisterInfo.h"
#include "SparcV8Subtarget.h"
#include "Sparc.h"
#include "SparcRegisterInfo.h"
#include "SparcSubtarget.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@ -22,100 +22,100 @@
#include <iostream>
using namespace llvm;
SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st)
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
V8::ADJCALLSTACKUP), Subtarget(st) {
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
Subtarget(st) {
}
void SparcV8RegisterInfo::
void SparcRegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FI,
const TargetRegisterClass *RC) const {
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == V8::IntRegsRegisterClass)
BuildMI(MBB, I, V8::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
else if (RC == V8::FPRegsRegisterClass)
BuildMI(MBB, I, V8::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
else if (RC == V8::DFPRegsRegisterClass)
BuildMI(MBB, I, V8::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
else
assert(0 && "Can't store this register to stack slot");
}
void SparcV8RegisterInfo::
void SparcRegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
if (RC == V8::IntRegsRegisterClass)
BuildMI(MBB, I, V8::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
else if (RC == V8::FPRegsRegisterClass)
BuildMI(MBB, I, V8::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
else if (RC == V8::DFPRegsRegisterClass)
BuildMI(MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
else
assert(0 && "Can't load this register from stack slot");
}
void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
if (RC == V8::IntRegsRegisterClass)
BuildMI(MBB, I, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(SrcReg);
else if (RC == V8::FPRegsRegisterClass)
BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
else if (RC == V8::DFPRegsRegisterClass)
BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD,
void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
1, DestReg).addReg(SrcReg);
else
assert (0 && "Can't copy this register");
}
MachineInstr *SparcV8RegisterInfo::foldMemoryOperand(MachineInstr* MI,
unsigned OpNum,
int FI) const {
MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
unsigned OpNum,
int FI) const {
bool isFloat = false;
switch (MI->getOpcode()) {
case V8::ORrr:
if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == V8::G0&&
case SP::ORrr:
if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
if (OpNum == 0) // COPY -> STORE
return BuildMI(V8::STri, 3).addFrameIndex(FI).addImm(0)
return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
.addReg(MI->getOperand(2).getReg());
else // COPY -> LOAD
return BuildMI(V8::LDri, 2, MI->getOperand(0).getReg())
return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
.addFrameIndex(FI).addImm(0);
}
break;
case V8::FMOVS:
case SP::FMOVS:
isFloat = true;
// FALLTHROUGH
case V8::FMOVD:
case SP::FMOVD:
if (OpNum == 0) // COPY -> STORE
return BuildMI(isFloat ? V8::STFri : V8::STDFri, 3)
return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
.addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
else // COPY -> LOAD
return BuildMI(isFloat ? V8::LDFri : V8::LDDFri, 2,
return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2,
MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
break;
}
return 0;
}
void SparcV8RegisterInfo::
void SparcRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
MachineInstr &MI = *I;
int Size = MI.getOperand(0).getImmedValue();
if (MI.getOpcode() == V8::ADJCALLSTACKDOWN)
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
BuildMI(MBB, I, V8::ADDri, 2, V8::O6).addReg(V8::O6).addSImm(Size);
BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size);
MBB.erase(I);
}
void
SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
unsigned i = 0;
MachineInstr &MI = *II;
while (!MI.getOperand(i).isFrameIndex()) {
@ -134,27 +134,27 @@ SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
if (Offset >= -4096 && Offset <= 4095) {
// If the offset is small enough to fit in the immediate field, directly
// encode it.
MI.SetMachineOperandReg(i, V8::I6);
MI.SetMachineOperandReg(i, SP::I6);
MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
} else {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
unsigned OffHi = (unsigned)Offset >> 10U;
BuildMI(*MI.getParent(), II, V8::SETHIi, 1, V8::G1).addImm(OffHi);
BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
BuildMI(*MI.getParent(), II, V8::ADDrr, 2,
V8::G1).addReg(V8::G1).addReg(V8::I6);
BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
SP::G1).addReg(SP::G1).addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
MI.SetMachineOperandReg(i, V8::G1);
MI.SetMachineOperandReg(i, SP::G1);
MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
Offset & ((1 << 10)-1));
}
}
void SparcV8RegisterInfo::
void SparcRegisterInfo::
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -175,29 +175,29 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
NumBytes = -NumBytes;
if (NumBytes >= -4096) {
BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
V8::O6).addImm(NumBytes).addReg(V8::O6);
BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
SP::O6).addImm(NumBytes).addReg(SP::O6);
} else {
MachineBasicBlock::iterator InsertPt = MBB.begin();
// Emit this the hard way. This clobbers G1 which we always know is
// available here.
unsigned OffHi = (unsigned)NumBytes >> 10U;
BuildMI(MBB, InsertPt, V8::SETHIi, 1, V8::G1).addImm(OffHi);
BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
BuildMI(MBB, InsertPt, V8::ORri, 2, V8::G1)
.addReg(V8::G1).addImm(NumBytes & ((1 << 10)-1));
BuildMI(MBB, InsertPt, V8::SAVErr, 2,
V8::O6).addReg(V8::O6).addReg(V8::G1);
BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
BuildMI(MBB, InsertPt, SP::SAVErr, 2,
SP::O6).addReg(SP::O6).addReg(SP::G1);
}
}
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == V8::RETL &&
assert(MBBI->getOpcode() == SP::RETL &&
"Can only put epilog before 'retl' instruction!");
BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
}
#include "SparcV8GenRegisterInfo.inc"
#include "SparcGenRegisterInfo.inc"

18
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -1,4 +1,4 @@
//===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
//===- SparcRegisterInfo.h - Sparc Register Information Impl ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,25 +7,25 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
// This file contains the Sparc implementation of the MRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef SPARCV8REGISTERINFO_H
#define SPARCV8REGISTERINFO_H
#ifndef SPARCREGISTERINFO_H
#define SPARCREGISTERINFO_H
#include "llvm/Target/MRegisterInfo.h"
#include "SparcV8GenRegisterInfo.h.inc"
#include "SparcGenRegisterInfo.h.inc"
namespace llvm {
class SparcV8Subtarget;
class SparcSubtarget;
class Type;
struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
SparcV8Subtarget &Subtarget;
struct SparcRegisterInfo : public SparcGenRegisterInfo {
SparcSubtarget &Subtarget;
SparcV8RegisterInfo(SparcV8Subtarget &st);
SparcRegisterInfo(SparcSubtarget &st);
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,

16
lib/Target/Sparc/SparcRegisterInfo.td
View File

@ -1,4 +1,4 @@
//===- SparcV8RegisterInfo.td - SparcV8 Register defs ------*- tablegen -*-===//
//===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -8,12 +8,12 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Declarations that describe the SparcV8 register file
// Declarations that describe the Sparc register file
//===----------------------------------------------------------------------===//
class SparcReg<string n> : Register<n> {
field bits<5> Num;
let Namespace = "V8";
let Namespace = "SP";
}
// Registers are identified with 5-bit ID numbers.
@ -69,11 +69,11 @@ def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>;
def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
/// Integer and FP Condition codes.
let Namespace = "V8" in {
let Namespace = "SP" in {
def ICC : Register<"ICC">;
def FCC : Register<"FCC">;
}
def FLAGS_REGS : RegisterClass<"V8", [FlagVT], 32, [ICC, FCC]> {
def FLAGS_REGS : RegisterClass<"SP", [FlagVT], 32, [ICC, FCC]> {
let Size = 32;
}
@ -82,7 +82,7 @@ def FLAGS_REGS : RegisterClass<"V8", [FlagVT], 32, [ICC, FCC]> {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
O0, O1, O2, O3, O4, O5, O7,
@ -110,9 +110,9 @@ def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
}];
}
def FPRegs : RegisterClass<"V8", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def DFPRegs : RegisterClass<"V8", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7,
def DFPRegs : RegisterClass<"SP", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15]>;

8
lib/Target/Sparc/SparcSubtarget.cpp
View File

@ -1,4 +1,4 @@
//===- SparcV8Subtarget.cpp - SPARC Subtarget Information -----------------===//
//===- SparcSubtarget.cpp - SPARC Subtarget Information -------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
#include "SparcV8Subtarget.h"
#include "SparcV8GenSubtarget.inc"
#include "SparcSubtarget.h"
#include "SparcGenSubtarget.inc"
using namespace llvm;
// FIXME: temporary.
@ -22,7 +22,7 @@ namespace {
cl::desc("Enable V9 instructions in the V8 target"));
}
SparcV8Subtarget::SparcV8Subtarget(const Module &M, const std::string &FS) {
SparcSubtarget::SparcSubtarget(const Module &M, const std::string &FS) {
// Set the default features.
IsV9 = false;
V8DeprecatedInsts = false;

6
lib/Target/Sparc/SparcSubtarget.h
View File

@ -1,4 +1,4 @@
//=====-- SparcV8Subtarget.h - Define Subtarget for the SPARC -*- C++ -*--====//
//=====-- SparcSubtarget.h - Define Subtarget for the SPARC ----*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
@ -20,12 +20,12 @@
namespace llvm {
class Module;
class SparcV8Subtarget : public TargetSubtarget {
class SparcSubtarget : public TargetSubtarget {
bool IsV9;
bool V8DeprecatedInsts;
bool IsVIS;
public:
SparcV8Subtarget(const Module &M, const std::string &FS);
SparcSubtarget(const Module &M, const std::string &FS);
bool isV9() const { return IsV9; }
bool isVIS() const { return IsVIS; }

36
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -1,4 +1,4 @@
//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
//
// The LLVM Compiler Infrastructure
//
@ -10,8 +10,8 @@
//
//===----------------------------------------------------------------------===//
#include "SparcV8TargetMachine.h"
#include "SparcV8.h"
#include "SparcTargetMachine.h"
#include "Sparc.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
@ -26,20 +26,19 @@ using namespace llvm;
namespace {
// Register the target.
RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
RegisterTarget<SparcTargetMachine> X("sparc", " SPARC");
}
/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
/// SparcTargetMachine ctor - Create an ILP32 architecture model
///
SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
IntrinsicLowering *IL,
const std::string &FS)
: TargetMachine("SparcV8", IL, false, 4, 4),
SparcTargetMachine::SparcTargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS)
: TargetMachine("Sparc", IL, false, 4, 4),
Subtarget(M, FS), InstrInfo(Subtarget),
FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
}
unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) {
std::string TT = M.getTargetTriple();
if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "sparc-")
return 20;
@ -47,7 +46,7 @@ unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
if (M.getEndianness() == Module::BigEndian &&
M.getPointerSize() == Module::Pointer32)
#ifdef __sparc__
return 20; // BE/32 ==> Prefer sparcv8 on sparc
return 20; // BE/32 ==> Prefer sparc on sparc
#else
return 5; // BE/32 ==> Prefer ppc elsewhere
#endif
@ -61,10 +60,9 @@ unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
/// addPassesToEmitFile - Add passes to the specified pass manager
/// to implement a static compiler for this target.
///
bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
std::ostream &Out,
CodeGenFileType FileType,
bool Fast) {
bool SparcTargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
CodeGenFileType FileType,
bool Fast) {
if (FileType != TargetMachine::AssemblyFile) return true;
// FIXME: Implement efficient support for garbage collection intrinsics.
@ -83,7 +81,7 @@ bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
PM.add(createSparcV8ISelDag(*this));
PM.add(createSparcISelDag(*this));
// Print machine instructions as they were initially generated.
if (PrintMachineCode)
@ -97,16 +95,16 @@ bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));
PM.add(createSparcV8FPMoverPass(*this));
PM.add(createSparcFPMoverPass(*this));
PM.add(createSparcV8DelaySlotFillerPass(*this));
PM.add(createSparcDelaySlotFillerPass(*this));
// Print machine instructions after filling delay slots.
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));
// Output assembly language.
PM.add(createSparcV8CodePrinterPass(Out, *this));
PM.add(createSparcCodePrinterPass(Out, *this));
// Delete the MachineInstrs we generated, since they're no longer needed.
PM.add(createMachineCodeDeleter());

24
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -1,4 +1,4 @@
//===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,33 +7,33 @@
//
//===----------------------------------------------------------------------===//
//
// This file declares the SparcV8 specific subclass of TargetMachine.
// This file declares the Sparc specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
#ifndef SPARCV8TARGETMACHINE_H
#define SPARCV8TARGETMACHINE_H
#ifndef SPARCTARGETMACHINE_H
#define SPARCTARGETMACHINE_H
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/PassManager.h"
#include "SparcV8InstrInfo.h"
#include "SparcV8Subtarget.h"
#include "SparcInstrInfo.h"
#include "SparcSubtarget.h"
namespace llvm {
class IntrinsicLowering;
class Module;
class SparcV8TargetMachine : public TargetMachine {
SparcV8Subtarget Subtarget;
SparcV8InstrInfo InstrInfo;
class SparcTargetMachine : public TargetMachine {
SparcSubtarget Subtarget;
SparcInstrInfo InstrInfo;
TargetFrameInfo FrameInfo;
public:
SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS);
SparcTargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS);
virtual const SparcV8InstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual const MRegisterInfo *getRegisterInfo() const {