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ARM assembly parsing and encoding for SMC instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-22 18:13:31 +00:00
parent 7931df3d74
commit 7c9fbc0340
3 changed files with 12 additions and 3 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
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@ -1742,8 +1742,8 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
// Secure Monitor Call is a system instruction -- for disassembly only
def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
[/* For disassembly only; pattern left blank */]> {
def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
[]> {
bits<4> opt;
let Inst{23-4} = 0b01100000000000000111;
let Inst{3-0} = opt;

2
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3170,7 +3170,7 @@ def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
// Secure Monitor Call is a system instruction -- for disassembly only
// Option = Inst{19-16}
def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26-20} = 0b1111111;

9
test/MC/ARM/basic-arm-instructions.s
View File

@ -1359,6 +1359,15 @@ _func:
@ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6]
@ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6]
@------------------------------------------------------------------------------
@ SMC
@------------------------------------------------------------------------------
smc #0xf
smceq #0
@ CHECK: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1]
@ CHECK: smceq #0 @ encoding: [0x70,0x00,0x60,0x01]
@------------------------------------------------------------------------------
@ STM*