From 7ca2a7d7421c28422871dab575322bc45c848542 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sat, 23 Aug 2014 23:21:04 +0000 Subject: [PATCH] [PowerPC] Add support for dcbtst and icbt (prefetch) Adds code generation support for dcbtst (data cache prefetch for write) and icbt (instruction cache prefetch for read - Book E cores only). We still end up with a 'cannot select' error for the non-supported prefetch intrinsic forms. This will be fixed in a later commit. Fixes PR20692. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216339 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrFormats.td | 15 +++++++++++ lib/Target/PowerPC/PPCInstrInfo.td | 9 ++++++- test/CodeGen/PowerPC/ppc64-prefetch.ll | 25 ++++++++++++++++--- .../PowerPC/ppc64-encoding-bookII.txt | 3 +++ test/MC/PowerPC/ppc64-encoding-bookII.s | 4 +++ 5 files changed, 52 insertions(+), 4 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 2da4257d9f7..aa6849744d2 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -478,6 +478,21 @@ class XForm_16 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = 0; } +class XForm_icbt opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I { + bits<4> CT; + bits<5> RA; + bits<5> RB; + + let Inst{6} = 0; + let Inst{7-10} = CT; + let Inst{11-15} = RA; + let Inst{16-20} = RB; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + class XForm_sr opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : I { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 3b2c7cb3d81..38020efb58b 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -1303,8 +1303,15 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; +def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), + "icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>; + def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), - (DCBT xoaddr:$dst)>; + (DCBT xoaddr:$dst)>; // data prefetch for loads +def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), + (DCBTST xoaddr:$dst)>; // data prefetch for stores +def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), + (ICBT 0, xoaddr:$dst)>; // inst prefetch (for read) // Atomic operations let usesCustomInserter = 1 in { diff --git a/test/CodeGen/PowerPC/ppc64-prefetch.ll b/test/CodeGen/PowerPC/ppc64-prefetch.ll index b2f37097f92..b2f6e7d6652 100644 --- a/test/CodeGen/PowerPC/ppc64-prefetch.ll +++ b/test/CodeGen/PowerPC/ppc64-prefetch.ll @@ -1,15 +1,34 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc < %s | FileCheck %s +; RUN: llc -mcpu=a2 < %s | FileCheck %s define void @test1(i8* %a, ...) nounwind { entry: call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1) ret void + +; CHECK-LABEL: @test1 +; CHECK: dcbt } declare void @llvm.prefetch(i8*, i32, i32, i32) -; CHECK: @test1 -; CHECK: dcbt +define void @test2(i8* %a, ...) nounwind { +entry: + call void @llvm.prefetch(i8* %a, i32 1, i32 3, i32 1) + ret void + +; CHECK-LABEL: @test2 +; CHECK: dcbtst +} + +define void @test3(i8* %a, ...) nounwind { +entry: + call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0) + ret void + +; CHECK-LABEL: @test3 +; CHECK: icbt +} + diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt index f0ef9024648..7a30b5cb2b6 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt @@ -3,6 +3,9 @@ # CHECK: icbi 2, 3 0x7c 0x02 0x1f 0xac +# CHECK: icbt 0, 5, 31 +0x7c 0x05 0xf8 0x2c + # CHECK: dcbt 2, 3 0x7c 0x02 0x1a 0x2c diff --git a/test/MC/PowerPC/ppc64-encoding-bookII.s b/test/MC/PowerPC/ppc64-encoding-bookII.s index fea2a3e46f2..20eba7083f6 100644 --- a/test/MC/PowerPC/ppc64-encoding-bookII.s +++ b/test/MC/PowerPC/ppc64-encoding-bookII.s @@ -8,6 +8,10 @@ # CHECK-LE: icbi 2, 3 # encoding: [0xac,0x1f,0x02,0x7c] icbi 2, 3 +# CHECK-BE: icbt 0, 5, 31 # encoding: [0x7c,0x05,0xf8,0x2c] +# CHECK-LE: icbt 0, 5, 31 # encoding: [0x2c,0xf8,0x05,0x7c] + icbt 0, 5, 31 + # FIXME: dcbt 2, 3, 10 # CHECK-BE: dcbt 2, 3 # encoding: [0x7c,0x02,0x1a,0x2c] # CHECK-LE: dcbt 2, 3 # encoding: [0x2c,0x1a,0x02,0x7c]