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Change the names of 64-bit logical instructions so that they match the names of
the real instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141718 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -133,18 +133,18 @@ def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
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def DANDi : LogicI64<0x0c, "andi", and>;
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def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
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def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
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def DORi : LogicI64<0x0d, "ori", or>;
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def DXORi : LogicI64<0x0e, "xori", xor>;
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def ORi64 : LogicI64<0x0d, "ori", or>;
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def XORi64 : LogicI64<0x0e, "xori", xor>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
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def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu>;
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def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
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def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
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def DAND : LogicR64<0x24, "and", and>;
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def DOR : LogicR64<0x25, "or", or>;
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def DXOR : LogicR64<0x26, "xor", xor>;
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def DNOR : LogicNOR64<0x00, 0x27, "nor">;
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def AND64 : LogicR64<0x24, "and", and>;
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def OR64 : LogicR64<0x25, "or", or>;
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def XOR64 : LogicR64<0x26, "xor", xor>;
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def NOR64 : LogicNOR64<0x00, 0x27, "nor">;
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/// Shift Instructions
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def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
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@ -226,7 +226,7 @@ def DCLO : CountLeading64<0x25, "dclo",
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def : Pat<(i64 immSExt16:$in),
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(DADDiu ZERO_64, imm:$in)>;
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def : Pat<(i64 immZExt16:$in),
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(DORi ZERO_64, imm:$in)>;
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(ORi64 ZERO_64, imm:$in)>;
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// zextloadi32_u
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def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
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@ -241,7 +241,7 @@ defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
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ZERO_64>;
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// setcc patterns
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defm : SeteqPats<CPU64Regs, SLTiu64, DXOR, SLTu64, ZERO_64>;
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defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
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